8251 USART

The 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter) is a programmable serial communication interface IC designed to connect a microprocessor system to serial peripherals such as modems, terminals, and printers. It handles the conversion between parallel data (used internally by the CPU) and serial data (used on transmission lines), along with framing, error detection, and flow control. This IC is a standard topic in microprocessor interfacing for university exams and GATE.

Core Concept Explanation

The 8251 performs full-duplex serial communication, meaning it can simultaneously transmit and receive data. The CPU writes 8-bit parallel data into the Transmit Buffer, which is loaded into the Transmit Shift Register. The shift register then sends bits serially on the TxD pin, one bit per clock period. On the receive side, incoming serial bits on RxD are shifted into the Receive Shift Register, assembled into a full byte, and then moved to the Receive Buffer for the CPU to read.

The C/D (Control/Data) pin determines whether the CPU is accessing a data register or a control/status register. When C/D = 0, the CPU reads or writes data. When C/D = 1, a write goes to the Command or Mode register and a read returns the Status register. This pin-sharing is important for interfacing: A0 of the CPU address bus is typically connected to C/D.

The 8251 must be initialized by software before use. After a hardware reset or software reset, the CPU must first write a Mode word that defines the communication format. After the Mode word, subsequent writes to C/D=1 go to the Command register. The initialization sequence is: reset, write Mode word, write Command word, then begin data transfers.

Asynchronous Mode

In asynchronous mode, each character is framed independently with a Start bit (logic 0), 5 to 8 data bits, an optional parity bit, and 1, 1.5, or 2 Stop bits (logic 1). The receiver detects the falling edge of the Start bit and then samples data bits at the center of each bit period. The baud rate clock (TxC/RxC) is typically 1x, 16x, or 64x the actual baud rate, as programmed in the Mode word.

If the Mode word baud rate factor is 16x, then for a 9600 baud transmission, the TxC and RxC clock inputs must be supplied at 9600 x 16 = 153,600 Hz. The 16x oversampling allows the receiver to tolerate small frequency mismatches between transmitter and receiver clocks.

Synchronous Mode

In synchronous mode, there are no Start and Stop bits. Data is transmitted as a continuous stream. The transmitter inserts special SYNC characters (1 or 2 bytes programmed into the SYNC register) when no actual data is available, to maintain clock synchronization at the receiver. The receiver hunts for the SYNC character pattern (SYNDET goes high when sync is achieved). In synchronous mode, the baud rate factor in the Mode word must be set to 1x since the clock is already at the exact baud rate.

Mode Word and Command Word Format

The 8-bit Mode Word for asynchronous mode encodes: D1-D0 (baud rate factor: 01=1x, 10=16x, 11=64x), D3-D2 (character length: 00=5 bits, 11=8 bits), D4 (parity enable), D5 (even/odd parity), D7-D6 (stop bits: 01=1, 10=1.5, 11=2). The Mode Word is written only once after reset.

The 8-bit Command Word controls operational aspects: D0 (TxEN, enable transmitter), D1 (DTR, Data Terminal Ready output), D2 (RxEN, enable receiver), D3 (SBRK, send break), D4 (ER, reset error flags), D5 (RTS, Request To Send), D6 (IR, internal reset), D7 (EH, enter hunt mode for sync). Most interfacing problems require TxEN and RxEN to be set for basic operation.

Mathematical Expression

In asynchronous mode, the actual bit time T_bit = 1 / baud_rate. For N data bits plus framing overhead (1 start + P parity + S stop bits), the total bits per character = 1 + N + P + S. The effective data throughput in characters per second is: CPS = baud_rate / (1 + N + P + S).

Given:
Baud rate = 9600 bps
Data bits = 8
Parity = 1 (odd parity)
Stop bits = 1
Baud rate factor (Mode word) = 16x

Why this formula applies:
Total bits per character includes start, data, parity, and stop bits.

Formula:
CPS = baud_rate / (1 + data_bits + parity_bits + stop_bits)
Required TxC/RxC = baud_rate x baud_factor

Substitution:
CPS = 9600 / (1 + 8 + 1 + 1)
Required TxC/RxC = 9600 x 16

Calculation:
CPS = 9600 / 11 = 872.7 characters per second
Required TxC/RxC = 153,600 Hz

Final Answer:
Throughput = 872.7 characters/second. Supply 153.6 kHz to TxC and RxC pins.

Exam Tip: The 8251 Mode word is written exactly once after reset; all subsequent writes to C/D=1 go to the Command register. In synchronous mode the baud rate factor bits must be 00 (not 01). TxRDY and RxRDY status bits are used for polling; TxRDY goes high when the transmit buffer is empty, and RxRDY goes high when a received byte is ready.

Practical Understanding

The 8251 was the standard serial interface IC in 8085 and 8086 based systems for connecting terminals, printers, and modems. It implements the fundamental concepts still relevant in modern UARTs: framing format, baud rate generation, oversampling, and modem control signals (DTR, RTS, DSR, CTS). Modern microcontrollers contain built-in USART peripherals that operate on identical principles to the 8251.

The TxRDY and RxRDY status bits can be used in polling mode (CPU reads Status register and checks bits) or connected to interrupt inputs for interrupt-driven communication. Interrupt-driven transfers are more efficient than polled transfers since the CPU can do other work between character transmissions at lower baud rates.

Mechanism: Serial Frame Structure

• Line is held HIGH (mark) during idle. A falling edge on TxD signals the Start bit, alerting the receiver to begin sampling.
• Data bits D0 through D7 are sent LSB first, each lasting exactly 1 / baud_rate seconds.
• An optional parity bit follows the data bits for error detection. The 8251 hardware computes and checks parity automatically.
• One or more Stop bits (HIGH) terminate the character, providing a guaranteed idle gap before the next Start bit.
• Error flags in the Status register: PE (Parity Error), OE (Overrun Error, CPU did not read before next char arrived), FE (Framing Error, Stop bit not detected). These are cleared by writing ER bit in Command word.

Quick Revision

• 8251 is a full-duplex USART supporting both synchronous and asynchronous serial communication.
• C/D pin: 0 = data access, 1 = control/status access. Initialization order: reset, Mode word, Command word.
• Async mode: Start (0) + D0-D7 + Parity + Stop (1). Baud factor: 1x, 16x, or 64x applied to TxC/RxC.
• Sync mode: SYNC characters replace framing. Baud factor must be 1x. SYNDET indicates sync achieved.
• CPS = baud_rate / total_bits_per_character. TxC/RxC = baud_rate x baud_factor.
• TxRDY: transmit buffer empty. RxRDY: received byte ready. Both can drive interrupts.
• Exam trap: Mode word is written only once after reset. Second write to C/D=1 goes to Command register, not Mode register again.