Evolution to Pentium

The journey from the Intel 8086 to the Pentium family represents one of the most significant progressions in microprocessor architecture. Each generation introduced fundamental improvements in data width, address space, clock speed, and internal architecture. Understanding this evolution helps in grasping why modern processors are designed the way they are.

For GATE aspirants and engineering students, this topic covers comparative features of the 286, 386, 486, and Pentium processors, including their bus widths, memory addressing capabilities, and architectural innovations that distinguish each generation.

Core Concept: Why Processors Evolved

Each processor generation was driven by a need to handle larger programs, faster computations, and more memory. The primary axes of improvement were the data bus width (how many bits are transferred per cycle), the address bus width (how much memory can be addressed), clock frequency, and the number of functional units inside the chip.

The 8086 was a 16-bit processor with a 20-bit address bus, allowing access to 2^20 = 1 MB of memory. The 80286 kept the 16-bit data bus but extended the address bus to 24 bits, expanding addressable memory to 16 MB and introducing protected mode for multitasking operating systems.

The 80386: First True 32-bit Processor

The 80386 was a landmark because it was the first processor to implement a fully 32-bit internal and external architecture. Both the data bus and address bus became 32 bits wide, enabling access to 4 GB of physical memory. It also introduced Virtual 8086 Mode, which allowed older 8086 programs to run inside a protected-mode operating system without conflict.

The 386 also introduced paging as a hardware mechanism for virtual memory management. Paging allows the operating system to use disk space as an extension of RAM by mapping virtual addresses to physical addresses through page tables. This was a fundamental requirement for modern operating systems like Unix and Windows NT.

The 80486: Integration and Pipelining

The 80486 retained the 32-bit architecture of the 386 but made major internal changes. It integrated the Floating Point Unit (FPU) directly onto the processor die, eliminating the need for a separate 80387 math coprocessor. This reduced latency for floating-point operations significantly.

The 486 also introduced an 8 KB on-chip L1 cache and a 5-stage integer pipeline. The pipeline allowed one instruction to complete per clock cycle under ideal conditions, doubling effective throughput compared to the 386 at the same clock frequency. At 25 MHz, a 486 significantly outperformed a 386 at the same speed.

The Pentium: Superscalar Architecture

The Pentium processor (P5, 1993) introduced the superscalar architecture to the x86 family. It has two parallel integer execution pipelines called the U-pipe and V-pipe. Under favorable conditions, two instructions can be issued and executed simultaneously per clock cycle, making the Pentium a true superscalar processor.

The Pentium also widened the external data bus to 64 bits while keeping the internal 32-bit registers for backward compatibility. This 64-bit bus allows two 32-bit words to be fetched from memory in one bus transaction, improving memory bandwidth significantly. Separate 8 KB instruction and data caches were also included to reduce cache conflicts.

Mathematical Expression

The addressable memory is directly computed from the address bus width using the formula: Addressable Memory = 2^N bytes, where N is the number of address lines. For the 8086 with N = 20, memory = 2^20 = 1 MB. For the 386 with N = 32, memory = 2^32 = 4 GB. Doubling N adds exponentially more memory capacity.

Given:
8086 address bus = 20 bits
80286 address bus = 24 bits
80386 address bus = 32 bits

Why this formula applies:
Each address line doubles the addressable locations.

Formula:
Addressable Memory = 2^N bytes

Substitution:
8086: 2^20 = 1,048,576 bytes = 1 MB
80286: 2^24 = 16,777,216 bytes = 16 MB
80386: 2^32 = 4,294,967,296 bytes = 4 GB

Calculation:
2^20 = 1 MB, 2^24 = 16 MB, 2^32 = 4 GB

Final Answer: Each 4-bit increase in address bus multiplies addressable memory by 16x.

Exam Tip: Remember the address bus widths: 8086=20bit (1MB), 286=24bit (16MB), 386/486/Pentium=32bit (4GB). The Pentium's data bus is 64-bit but its registers and address bus remain 32-bit.

• 8086: 16-bit data, 20-bit address (1 MB), real mode only.
• 286: 16-bit data, 24-bit address (16 MB), added protected mode.
• 386: 32-bit data and address (4 GB), paging, Virtual 8086 Mode.
• 486: Integrated FPU, 8 KB L1 cache, 5-stage pipeline, single-cycle throughput.
• Pentium: 64-bit external bus, dual U/V pipelines, superscalar, separate I/D caches.

Quick Revision

• Address bus determines max RAM: 2^N bytes where N = number of address lines.
• 8086 = 1 MB, 286 = 16 MB, 386/486/Pentium = 4 GB addressable.
• 386 was first full 32-bit processor with paging support.
• 486 integrated FPU on chip and introduced L1 cache with 5-stage pipeline.
• Pentium data bus is 64-bit externally but registers are 32-bit (backward compatible).
• Pentium has two integer pipelines (U and V) for superscalar execution.
• Exam trap: Pentium has 64-bit data bus but 32-bit internal registers and address bus.