8253/54 Timer

The 8253/8254 is a Programmable Interval Timer (PIT) designed to generate accurate time delays, event counts, and square waves when interfaced with the 8085/8086 microprocessor. It is widely used in systems requiring precise timing without burdening the CPU with software delay loops. Understanding its internal structure and operating modes is essential for both practical interfacing and GATE preparation.

Core Concept Explanation

The 8253/8254 contains three independent 16-bit down counters (Counter 0, Counter 1, Counter 2). Each counter has three pins: CLK (clock input), GATE (enable/trigger), and OUT (output waveform). The CPU programs each counter by writing a control word to the Control Word Register, specifying which counter to use, the operating mode, and whether the count is in binary or BCD.

The chip is selected via CS (Chip Select) and addressed using A1 and A0 pins. A1=0, A0=0 selects Counter 0; A1=0, A0=1 selects Counter 1; A1=1, A0=0 selects Counter 2; A1=1, A0=1 selects the Control Word Register. The CPU writes the count value (called the count register) and then the counter decrements it on each CLK pulse, generating an output event when it reaches zero.

The 8254 is an enhanced version of the 8253. Both support 6 modes of operation, but the 8254 additionally allows the CPU to read the current count value (via read-back command) without disrupting the count. The 8254 also operates at higher clock frequencies (up to 10 MHz) compared to 8253 (up to 2.6 MHz).

Operating Modes

All six modes define how the OUT pin behaves relative to the count loaded and the GATE signal. These modes are critical for GATE exam questions and practical design.

• Mode 0 - Interrupt on Terminal Count: OUT goes HIGH when count reaches zero. GATE must be HIGH for counting to proceed. Used for one-shot software delays.
• Mode 1 - Hardware Retriggerable One-Shot: A rising edge on GATE triggers counting. OUT goes LOW for the programmed count duration. Retriggerable on each GATE pulse.
• Mode 2 - Rate Generator: OUT generates a periodic pulse (LOW for one CLK cycle) every N clock pulses. GATE HIGH enables counting. Used to generate periodic interrupts.
• Mode 3 - Square Wave Generator: OUT produces a square wave. For even count N, it is HIGH for N/2 and LOW for N/2 clocks. For odd N, it is HIGH for (N+1)/2 and LOW for (N-1)/2.
• Mode 4 - Software Triggered Strobe: Counting begins when count is written. OUT goes LOW for one CLK cycle when count reaches zero. Not retriggerable by GATE.
• Mode 5 - Hardware Triggered Strobe: Same as Mode 4 but triggered by a rising edge on GATE. OUT goes LOW for one CLK cycle at terminal count.

Control Word Format

The control word is an 8-bit value written to the Control Word Register. It determines the counter selection, read/load format, mode, and counting base. The format is: D7-D6 (SC1-SC0, select counter), D5-D4 (RL1-RL0, read/load format), D3-D1 (M2-M0, mode), D0 (BCD or binary). For RL bits: 00 = latch command, 01 = read/load LSB only, 10 = MSB only, 11 = LSB then MSB. Most practical uses require RL = 11 to load a 16-bit count.

Mathematical Expression

The output frequency and time period depend on the clock input and the count value N loaded into the counter. For Mode 2 (Rate Generator) and Mode 3 (Square Wave), the relationship is straightforward. If the input clock frequency is f_CLK and the count value is N, then the output frequency is:

f_OUT = f_CLK / N

This means the counter divides the input clock by N to produce the output. For a desired output frequency, the count value is computed as N = f_CLK / f_OUT. The count value N can range from 1 to 65536 (for 16-bit counters), where N = 0 is treated as 65536 in hardware.

Numerical Example

Consider a system where the 8253 is connected to a 2 MHz clock and needs to generate a 1 kHz square wave using Mode 3. The required count value N is calculated by dividing the clock frequency by the desired output frequency. This count is then loaded into the selected counter via the CPU.

Given:
f_CLK = 2 MHz = 2,000,000 Hz
f_OUT = 1 kHz = 1,000 Hz
Mode = 3 (Square Wave Generator)

Why this formula applies:
In Mode 3, the counter divides the input clock by N to produce a square wave.

Formula:
N = f_CLK / f_OUT

Substitution:
N = 2,000,000 / 1,000

Calculation:
N = 2000

Final Answer:
Load count value N = 2000 (decimal) = 07D0H into the counter.
Control word for Counter 0, Mode 3, LSB+MSB, Binary = 00 11 011 0 = 36H

Exam Tip: In GATE, Mode 2 and Mode 3 are the most tested. Remember that in Mode 3, for even N, duty cycle is exactly 50%. N=0 is treated as 65536 in 8253/8254 hardware, not as zero count. The control word address is always A1=1, A0=1 regardless of which counter is selected.

Practical Understanding

In PC-compatible systems, Counter 0 of the 8253/8254 was traditionally used to generate a periodic interrupt at 18.2 Hz (approximately) to drive the system clock tick. Counter 1 was used for DRAM refresh timing, and Counter 2 drove the PC speaker. This architecture illustrates how a single PIT chip handles multiple independent timing tasks simultaneously without any CPU intervention after initialization.

In GATE exam problems, you are often given a CLK frequency and asked to find the count value for a specific output frequency, or given a mode and asked to sketch the OUT waveform. Memorizing the behavior of OUT and GATE interaction for each mode is more important than memorizing control word bit positions.

Quick Revision

• 8253/8254 contains three independent 16-bit programmable down counters.
• Each counter has CLK, GATE, OUT pins. A1A0 = 11 selects Control Word Register.
• 6 modes: Mode 0 (interrupt on TC), Mode 1 (one-shot), Mode 2 (rate gen), Mode 3 (square wave), Mode 4 (SW strobe), Mode 5 (HW strobe).
• f_OUT = f_CLK / N for Mode 2 and Mode 3. N = 0 means 65536.
• 8254 enhancement over 8253: read-back command, higher clock frequency support.
• Control word format: SC1-SC0 | RL1-RL0 | M2-M1-M0 | BCD. RL=11 for full 16-bit load.
• Exam trap: GATE=LOW pauses counting in Mode 0 and Mode 2; in Mode 1 and Mode 5, GATE edge triggers counting.