8259 PIC

In a microprocessor system, multiple peripheral devices can request the CPU's attention simultaneously. Managing these requests in an orderly and prioritized manner is the function of the 8259 Programmable Interrupt Controller (PIC). The 8259 receives interrupt requests from up to eight devices, prioritizes them, and signals the 8086 CPU through a single INTR line with the appropriate interrupt vector. Understanding the 8259 is critical for real-time system design and is frequently tested in GATE.

Core Concept Explanation

The 8259 accepts interrupt requests on eight lines labeled IR0 through IR7. IR0 has the highest default priority and IR7 has the lowest. When a peripheral asserts one of these lines, the 8259 sets the corresponding bit in the Interrupt Request Register (IRR). The 8259 then checks the Interrupt Mask Register (IMR) to see if that interrupt is masked (disabled). If not masked, the priority resolver determines the highest priority pending interrupt and asserts INTR to the 8086.

The 8086 responds to INTR by completing its current instruction and then asserting INTA (Interrupt Acknowledge) twice. On the first INTA pulse, the 8259 sets the corresponding bit in the In-Service Register (ISR) and clears the IRR bit. This indicates the interrupt is being serviced. On the second INTA pulse, the 8259 places an 8-bit interrupt type number on the data bus. The 8086 uses this type number to look up the interrupt service routine (ISR) address in the Interrupt Vector Table.

The IMR (Interrupt Mask Register) is an 8-bit register where each bit corresponds to one IR line. Setting a bit to 1 masks (disables) the corresponding interrupt. The CPU can read and write the IMR at any time to selectively enable or disable specific interrupts without affecting others.

Initialization Command Words (ICWs)

Before the 8259 can operate, it must be initialized by writing a sequence of Initialization Command Words (ICWs). ICW1 is the first command and it triggers the initialization sequence. ICW1 specifies whether the trigger is edge or level, whether ICW4 is needed, and whether the 8259 is operating in single or cascaded mode.

ICW2 sets the base interrupt type number. The 8086 interrupt vector table has 256 entries (types 0 to 255). ICW2 sets bits T7-T3 of the type number. The lower 3 bits (T2-T0) are supplied by the 8259 based on which IR line caused the interrupt. So if ICW2 = 08H (00001000B) and IR3 is asserted, the type number = 00001000B with T2T1T0 = 011, giving type = 00001011B = 0BH.

ICW3 is used only in cascaded mode to identify which IR input of the master is connected to a slave. ICW4 enables 8086 mode (sets bit 0 to 1) and specifies automatic or normal EOI (End of Interrupt). In 8086 mode, the 8259 sends a full 8-bit interrupt type number on INTA. In 8085 mode, it sends a 3-byte CALL instruction. ICW4 must always be sent when using the 8259 with the 8086.

Operation Command Words (OCWs)

After initialization, the 8259 is controlled using Operation Command Words (OCWs). OCW1 is written to the IMR to mask or unmask specific interrupts. OCW2 issues various priority and EOI commands. The most important OCW2 command is the End of Interrupt (EOI) command (20H), which must be sent to the 8259 at the end of every ISR in non-automatic EOI mode. This clears the ISR bit and allows subsequent interrupts of equal or lower priority to be acknowledged.

OCW3 allows the CPU to read the IRR or ISR register and enables Special Mask Mode and Poll mode. In Poll mode, the CPU reads the 8259 to determine if an interrupt is pending, which is useful when INTR is not connected to the CPU.

Cascading 8259 PICs

A single 8259 handles 8 interrupt lines. If more than 8 interrupts are needed, multiple 8259s can be cascaded. In a cascaded configuration, one 8259 is designated the master and up to eight 8259s act as slaves. Each slave's INT output is connected to one of the master's IR inputs. The master's INTR output goes to the 8086. When a slave asserts an interrupt, the master passes it to the CPU. On the second INTA, the master signals the appropriate slave via a 3-bit CAS (cascade) bus, and the slave puts its interrupt type number on the data bus.

With one master and eight slaves, a total of 8 x 8 = 64 interrupt lines can be managed by the 8086. In a PC/XT system, two 8259s are cascaded to provide 15 usable interrupt lines (IR2 of the master connects to the slave, so that line is used for cascading and not available for peripherals).

Mathematical Expression

The interrupt type number generated by the 8259 is calculated as: Type Number = ICW2[7:3] concatenated with IR_number[2:0]. For example, if ICW2 = 20H = 0010 0000B and the interrupt is from IR5, then the type number = 00100 (from ICW2 bits 7-3) followed by 101 (binary for 5) = 00100101B = 25H. The ISR address is then fetched from the interrupt vector table at address 4 x Type Number.

Practical Understanding

In the original IBM PC, IRQ0 (connected to IR0 of the master 8259) is assigned to the system timer, IRQ1 to the keyboard, IRQ2 to the cascaded slave, and so on. This priority assignment ensures that the most time-critical device (timer) always gets the highest priority. The 8259 manages all of this transparently so the programmer only writes ISRs for each device type number.

Solved Example

An 8259 is initialized with ICW2 = 40H. Determine the interrupt type numbers for IR0 through IR7 and compute the ISR address in the vector table for IR3.

Given:
ICW2 = 40H = 0100 0000B
Bits 7-3 of ICW2 = 01000 (the upper 5 bits)

Why this formula applies:
Type Number = ICW2[7:3] concatenated with IR_number in 3-bit binary
ISR address in vector table = 4 x Type Number

Formula:
Type(IRn) = (ICW2 AND F8H) OR n

Substitution:
ICW2 AND F8H = 40H AND F8H = 40H = 0100 0000B

Calculation:
Type(IR0) = 40H | 0 = 40H
Type(IR1) = 40H | 1 = 41H
Type(IR2) = 40H | 2 = 42H
Type(IR3) = 40H | 3 = 43H
Type(IR4) = 40H | 4 = 44H
Type(IR5) = 40H | 5 = 45H
Type(IR6) = 40H | 6 = 46H
Type(IR7) = 40H | 7 = 47H

ISR address for IR3 (Type 43H = 67 decimal):
Vector Table Address = 4 x 67 = 268 decimal = 010CH

Final Answer:
IR3 generates interrupt type 43H.
ISR pointer is stored at address 010CH in the interrupt vector table.

Exam Tip: GATE frequently tests the type number formula. Always remember: upper 5 bits from ICW2, lower 3 bits from the IR line number. Also, EOI command (20H via OCW2) must be sent at end of ISR in normal EOI mode. Forgetting EOI means no further interrupts of equal or lower priority will be acknowledged.

Mechanism Diagram

Key Points on 8259 Operation

• IRR (Interrupt Request Register) captures pending interrupt requests from IR0-IR7.
• IMR (Interrupt Mask Register) selectively enables or disables individual IR lines. Bit = 1 means masked (disabled).
• ISR (In-Service Register) tracks which interrupt is currently being serviced. Set on first INTA, cleared by EOI.
• ICW sequence: ICW1 triggers init, ICW2 sets base type, ICW3 for cascading only, ICW4 for 8086 mode.
• EOI command (20H) must be sent at end of ISR in normal EOI mode to clear ISR bit.
• Cascading: slave INT connects to master IR pin. CAS bus selects slave on second INTA for type number output.

Quick Revision

• 8259 PIC manages 8 interrupt inputs (IR0 = highest priority, IR7 = lowest) and generates one INTR to CPU.
• Interrupt type number formula: Type = (ICW2 AND F8H) OR IR_number. Upper 5 bits from ICW2, lower 3 from IR line.
• ISR vector table address = 4 x Type Number (each entry is 4 bytes: IP + CS).
• ICW1: init trigger. ICW2: base type. ICW3: cascade IDs. ICW4: 8086 mode (bit 0 = 1).
• EOI = 20H via OCW2, sent at end of every ISR in normal EOI mode. GATE trap: missing EOI blocks lower priority ISRs.
• Cascading: 1 master + N slaves. PC/AT uses 1+1 = 15 usable IRQs. 1 master + 8 slaves = 64 maximum IRQs.
• IMR = 0FFH masks all interrupts. IMR = 00H unmasks all. Set individual bits to mask specific IR lines.