8086 Architecture

The Intel 8086 is a 16-bit microprocessor introduced in 1978 that became the foundation of the x86 architecture family still used in modern computers. Understanding 8086 architecture is essential for GATE aspirants because its internal organization, memory model, and pipelining approach introduce concepts that appear repeatedly across computer organization topics.

Core Concept: Two-Unit Architecture of 8086

The 8086 is internally divided into two independent units: the Bus Interface Unit (BIU) and the Execution Unit (EU). This separation allows the processor to perform a rudimentary form of pipelining, where the BIU fetches the next instruction from memory while the EU executes the current instruction. This overlap improves throughput compared to a single sequential fetch-execute cycle.

The BIU contains the four segment registers (CS, DS, SS, ES), the Instruction Pointer (IP), an internal 6-byte instruction queue (prefetch queue), and the address generation logic. Its primary function is to communicate with the external memory and I/O through the 16-bit data bus and 20-bit address bus.

The EU contains the general-purpose registers (AX, BX, CX, DX), the pointer and index registers (SP, BP, SI, DI), the ALU, and the Flag register. The EU receives instructions from the BIU queue rather than directly from memory, which is the source of the pipelining benefit. The EU never directly accesses the external bus; all memory and I/O requests go through the BIU.

Register Organization of 8086

The 8086 has fourteen 16-bit registers. The four general-purpose registers AX, BX, CX, and DX each have a specific conventional use: AX is the accumulator, BX is the base register for memory addressing, CX is the counter register used in loop and shift operations, and DX is the data register used in I/O operations and multiply/divide with extended precision.

Each of the four general registers can be split into two 8-bit halves. For example, AX consists of AH (high byte) and AL (low byte), allowing byte-level operations without affecting the full word. This split is unique to the general registers; pointer and index registers cannot be split.

The pointer registers SP (Stack Pointer) and BP (Base Pointer) operate with the SS (Stack Segment) register. The index registers SI (Source Index) and DI (Destination Index) are used in string operations. The Flag register holds 9 active flags out of 16 bits, including CF, PF, AF, ZF, SF, TF, IF, DF, and OF.

20-Bit Address Bus and 1 MB Memory Space

Although 8086 registers are 16-bit, the processor needs to address up to 1 MB of memory (2^20 = 1,048,576 bytes). This is achieved through the segmented memory model. A physical address is formed by shifting the segment register value 4 bits left (equivalent to multiplying by 16) and adding the 16-bit offset. The formula is:

Physical Address = Segment Register x 16 + Offset. For example, if CS = 2000H and IP = 0500H, then Physical Address = 20000H + 0500H = 20500H. This gives 20-bit addresses from two 16-bit values, enabling 1 MB addressability.

Instruction Queue and Pipelining

The BIU maintains a 6-byte instruction prefetch queue. While the EU executes an instruction, the BIU fills the queue with upcoming instruction bytes from memory. When the EU finishes the current instruction, it immediately fetches the next bytes from the queue without waiting for a memory access. This reduces effective instruction fetch time and increases overall processor throughput.

The queue is flushed whenever a branch instruction is executed, because the prefetched bytes after a branch are from the wrong address. After a branch, the BIU restarts fetching from the branch target, temporarily losing the pipeline benefit. This is why branching has a higher effective cost in pipelined processors.

Given:
CS = 3000H, IP = 0250H
Calculate the physical address of the next instruction.

Why this formula applies:
8086 uses segmented addressing: 20-bit physical address from 16-bit segment and offset.

Formula:
Physical Address (PA) = CS x 10H + IP

Substitution:
CS x 10H = 3000H x 10H = 30000H
IP = 0250H

Calculation:
PA = 30000H + 0250H = 30250H

Final Answer with units:
Physical Address = 30250H (hexadecimal), which is memory location 197,200 in decimal.

Exam Tip: 8086 physical address calculation is a guaranteed 1-2 mark question. Remember: segment x 10H (append a zero hex digit) + offset = physical address. The segment register itself is NOT the base address; you must multiply by 16 first. Confusing segment value with base address is the most common mistake.

BIU vs EU: Key Functional Differences

• BIU handles all external bus activity: instruction fetch, memory read/write, and I/O operations.
• EU executes instructions using its internal registers and ALU, sourcing instruction bytes from the BIU queue.
• Both units operate simultaneously in a pipelined fashion; EU executes while BIU prefetches.
• A branch or jump instruction flushes the prefetch queue, causing a pipeline stall until new bytes are fetched.
• 16-bit data bus means 8086 can transfer 2 bytes per bus cycle; odd-address word access requires two bus cycles.

Quick Revision

• 8086 = 16-bit data bus + 20-bit address bus = 1 MB addressable memory space.
• Two internal units: BIU (bus and prefetch) and EU (execute); operate in pipeline fashion.
• Physical Address = Segment x 16 + Offset (segment x 10H in hex).
• AX, BX, CX, DX are 16-bit general registers, each splittable into AH/AL, BH/BL, CH/CL, DH/DL.
• Segment registers: CS (code), DS (data), SS (stack), ES (extra data).
• Instruction prefetch queue = 6 bytes; flushed on every branch/jump.
• Trap: segment register is NOT the physical base; always multiply by 16 (or shift left by 4 bits).