8085 Pin Description

The 8085 microprocessor is housed in a 40-pin DIP (Dual Inline Package) and every pin serves a specific functional role in communicating with memory, I/O devices, power supply, and control circuits. A thorough understanding of the pin description is essential not only for hardware interfacing but also for interpreting timing diagrams and understanding how the processor manages its multiplexed bus. GATE and university examinations frequently test knowledge of specific pin functions, particularly the multiplexed address/data bus and control signal behavior.

Core Concept Explanation

The 8085 requires a 16-bit address bus to access 64KB of memory. However, to reduce chip pin count from 40 to a manageable number, Intel chose to multiplex the lower 8 address lines (A0 through A7) with the 8 data lines (D0 through D7) on the same physical pins, labeled AD0 through AD7. This multiplexing means that during the first clock state (T1) of every machine cycle, the pins carry an address, while during subsequent states (T2 and T3) the same pins carry data. External circuitry must latch the address during T1 before the bus transitions to data.

The upper 8 address bits, A8 through A15, are available on dedicated pins that are not shared with data. These pins carry only address information and do not require any external demultiplexing. Together, AD0-AD7 (after latching) and A8-A15 form the complete 16-bit address bus needed to address 64KB of memory space.

The ALE (Address Latch Enable) pin is the key to demultiplexing. It goes high at the beginning of every machine cycle (T1 state) to signal that the AD0-AD7 pins currently carry a valid address. An external 8-bit latch such as the 74LS373 or Intel 8212 uses ALE as its strobe input to capture and hold A0-A7. When ALE returns low, the latch holds the address while the bus transitions to data. Without this external latch, the address information would be lost.

Pin Groups and Their Functions

The power supply pins are VCC (pin 40, +5V) and GND (pin 20). The crystal oscillator pins X1 and X2 accept a crystal or RC network to generate the internal clock. The 8085 internally divides the crystal frequency by 2 to produce the operating clock. A 6 MHz crystal produces a 3 MHz internal clock. The CLK OUT pin provides this divided clock to other chips in the system.

The interrupt pins include TRAP (non-maskable, highest priority), RST 7.5, RST 6.5, RST 5.5 (all maskable, level triggered for 6.5 and 5.5, edge and level for 7.5), and INTR (general maskable interrupt). TRAP is the most important for GATE because it is non-maskable, meaning it cannot be disabled by software and always vectors to memory address 0024H.

The DMA (Direct Memory Access) pins are HOLD and HLDA. An external DMA controller asserts HOLD to request control of the buses. The 8085 completes its current machine cycle, then tri-states all bus and control pins and asserts HLDA to acknowledge. The DMA controller then takes over the buses to transfer data directly to or from memory without CPU involvement. This is used in systems requiring high-speed data transfer.

The READY pin allows interfacing with slow memory or I/O devices. If READY is low when the 8085 samples it during T2, the processor inserts additional wait states (TW) before completing the memory access. Fast memory keeps READY permanently high, eliminating wait states.

Mathematical Expression

The addressable memory space is determined by the width of the address bus. With 16 address lines, the 8085 can address 2 raised to 16 equals 65536 unique locations, each holding 1 byte, giving a total memory space of 64 Kilobytes. The I/O address space is separate: the 8085 uses 8-bit I/O addresses (A0-A7, with A8-A15 carrying the same value), giving 256 input and 256 output port addresses.

Numerical Example

A common numerical problem involves computing the number of memory chips required to fill the 8085 address space, or determining the clock frequency from crystal specifications. Below is a crystal-to-clock-frequency calculation, which is a standard GATE question format.

Given:
Crystal frequency = 6.144 MHz connected to X1, X2 pins of 8085
CLK OUT frequency needed: ?

Why this formula applies:
The 8085 internally divides the crystal frequency by 2 to derive the operating clock.
CLK OUT reflects this divided frequency and drives peripheral chips.

Formula:
f_CLK = f_crystal / 2

Substitution:
f_CLK = 6.144 MHz / 2

Calculation:
f_CLK = 3.072 MHz ≈ 3 MHz

T-state duration = 1 / f_CLK = 1 / (3.072 × 10⁶)
T-state duration = 0.3255 µs ≈ 325.5 ns

Final Answer:
Operating clock frequency = 3.072 MHz
One T-state = 325.5 ns
For instruction with 13 T-states: execution time = 13 × 325.5 ns = 4.23 µs

Exam Tip: GATE frequently tests the priority order of 8085 interrupts: TRAP (highest) > RST 7.5 > RST 6.5 > RST 5.5 > INTR (lowest). Also remember: TRAP is non-maskable and edge+level triggered. The crystal frequency is DIVIDED BY 2 internally — if the question gives 6 MHz crystal, the clock is 3 MHz.

Pin Signal Behavior Summary

• AD0–AD7 carry the lower 8 address bits during T1 (ALE high) and data during T2 and T3. An external latch must capture A0–A7 before ALE falls.
• A8–A15 are dedicated address pins that remain stable throughout the machine cycle. No latching is required for these lines.
• RD (active low) indicates the processor wants to read data. WR (active low) indicates the processor wants to write data. Both are asserted during T2 and T3.
• IO/M (active high for I/O, active low for memory) distinguishes whether the current bus cycle is accessing memory or an I/O port. Combined with RD and WR, this gives four bus operations: memory read, memory write, IO read, IO write.
• RESET IN (active low) initializes the PC to 0000H and the processor starts execution from address 0000H. RESET OUT signals external peripherals that a reset has occurred.

Quick Revision

• AD0–AD7: multiplexed bus. During T1 = lower address byte (A0–A7). During T2/T3 = data byte. ALE separates the two phases.
• A8–A15: dedicated address lines, not multiplexed. Always carry upper byte of address during entire machine cycle.
• ALE goes high during T1 to indicate valid address on AD bus. External 74LS373 latches A0–A7 on falling edge of ALE.
• RD, WR are active-low control signals. IO/M high = I/O access; IO/M low = memory access.
• Crystal frequency ÷ 2 = operating clock. A 6 MHz crystal gives 3 MHz clock and 333 ns T-state duration.
• Interrupt priority: TRAP > RST7.5 > RST6.5 > RST5.5 > INTR. TRAP is non-maskable. INTR requires an external INTA acknowledge cycle.
• HOLD/HLDA: DMA handshake. HOLD request from DMA; HLDA acknowledge from 8085. CPU tri-states buses after completing current machine cycle.