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Contents

Microprocessors

8085 Architecture

8085 Architecture Overview 8085 Pin Description Timing Diagrams Control Signals Demultiplexing Bus

8085 Instructions

Addressing Modes Instruction Set Groups Stack Instructions Rotate Instructions 16-bit Arithmetic

8085 Programming

Assembly Language Basics Arithmetic Programs Looping and Indexing Stack and Subroutines BCD Arithmetic Time Delay Loops Code Conversion

8086 Architecture

8086 Architecture Memory Segmentation 8086 Pin Diagram Flag Register 8086 Instruction Queue

8086 Programming

8086 Addressing Modes 8086 Instruction Set String Instructions Interrupts DOS Function Calls BIOS Interrupts Macros vs Procedures Assembler Directives

Peripheral Interfacing

Memory Interfacing IO Interfacing 8255 PPI 8259 PIC 8253/54 Timer 8237 DMA 8251 USART 7 Segment Display Interface Stepper Motor Interface Keyboard Interfacing

Modern Processors

Evolution to Pentium Protected Mode Pipelining Cache Memory Virtual Memory Branch Prediction Multi-core Processors Hyper-Threading SIMD Instructions

Other Topics

RISC vs CISC Microcontroller Difference Bus Standards

Other Subjects

Analog Electronics Digital Electronics Signals & Systems Control Systems Electromagnetic Theory Digital Communication Analog Communication Network Analysis VLSI Design Verilog HDL Power Electronics Embedded Systems DSP Electronic Devices

Section Progress44%

4 of 9 articles

Cache Memory

L1, L2, L3 cache, hit/miss, mapping techniques.

Updated: 19 March 2026

9 min read

#Microprocessors

Cache Memory Quiz

Test your understanding of cache mapping techniques, hit ratio calculations, and cache hierarchy.

Question 1 of 3

Q1.A direct-mapped cache has 128 lines, each line holding 16 bytes. The main memory has a 16-bit address. How many bits are used for the tag, set index, and block offset respectively?

Related Articles

Multi-core Processors

SMP, CMP, shared memory consistency.

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Hyper-Threading

SMT concepts.

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SIMD Instructions

MMX, SSE, AVX overview.

12 min read

Memory Interfacing

Address decoding, EPROM/RAM connection.

4 min read

Evolution to Pentium

286, 386, 486, Pentium features.

5 min read