8237 DMA

The 8237 Direct Memory Access (DMA) controller allows peripherals to transfer data directly to or from system memory without CPU intervention, significantly increasing data throughput. This is critical in systems where high-speed I/O devices like disk drives or ADC buffers would otherwise overload the CPU with repetitive data movement tasks. Understanding 8237 operation is a key topic in both university exams and GATE.

Core Concept Explanation

Without DMA, every byte transferred between a peripheral and memory requires the CPU to execute multiple instructions: read the peripheral status, read the data, write to memory, and update the address pointer. For a 1 MB file, this wastes millions of CPU cycles. The 8237 DMA controller replaces this by taking control of the address and data buses directly, transferring data in hardware at bus speed.

The 8237 contains four independent DMA channels (Ch 0 to Ch 3). Each channel has its own Base Address Register, Current Address Register, Base Word Count Register, and Current Word Count Register. The CPU programs these registers to specify where data should go (or come from) and how many bytes to transfer. Once programmed, the peripheral asserts DREQ and the 8237 takes over the bus.

The bus takeover sequence is called the DMA cycle. The 8237 asserts HRQ (Hold Request) to the CPU. The CPU finishes its current bus cycle, floats its address and data buses, and asserts HLDA (Hold Acknowledge). The 8237 then drives the address bus, asserts DACK (DMA Acknowledge) to the peripheral, and performs the memory transfer autonomously.

Transfer Modes

The 8237 supports four transfer modes programmed via the Mode Register. Each mode defines how the bus is held and how multiple bytes are transferred.

• Single Transfer Mode: One byte is transferred per DREQ assertion. After each byte, the bus is released to the CPU. DREQ must be re-asserted for the next byte. Slowest but fairest to CPU.
• Block Transfer Mode: The 8237 holds the bus until the entire programmed word count is transferred. CPU is locked out for the full block duration. Fastest throughput but CPU is stalled.
• Demand Transfer Mode: Data is transferred continuously while DREQ remains asserted. If DREQ drops, the 8237 saves state, releases the bus to CPU, and resumes when DREQ returns.
• Cascade Mode: Used to cascade multiple 8237 chips together for more than 4 channels. One 8237 acts as slave; its HRQ/HLDA connects to a master 8237 channel.

Transfer Types

Within each mode, three transfer types define the direction: Read Transfer (memory to I/O), Write Transfer (I/O to memory), and Verify Transfer (no actual data moved, just address incrementing for verification). Additionally, a Memory-to-Memory transfer is supported using Channels 0 and 1 together, where Channel 0 supplies source address and Channel 1 supplies destination address.

Address and Count Registers

Each channel has a 16-bit Current Address Register that is auto-incremented (or decremented if configured) after each transfer. The Current Word Count Register decrements after each byte. When the word count reaches FFFFh (underflow from 0000h), a Terminal Count (TC) signal is generated, indicating transfer completion. If Auto-initialize is enabled, the base registers are reloaded automatically into the current registers upon TC, making continuous circular buffer DMA possible.

Mathematical Expression

The word count register is programmed with N-1 if N bytes are to be transferred. This is because the counter decrements from the loaded value to 0000h and then to FFFFh triggers TC. So if you want to transfer 256 bytes, you load 255 (00FFh) into the word count register.

Number of bytes transferred = Word Count Register value + 1

The total DMA transfer time in Single Transfer Mode depends on the bus clock and number of DMA cycles: T_transfer = N x T_DMA_cycle, where T_DMA_cycle is typically 4 clock periods for the 8237.

Given:
Data block size = 512 bytes
Bus clock = 5 MHz
Transfer mode = Single Transfer
DMA cycle = 4 clock periods

Why this formula applies:
Each byte requires one complete DMA cycle of 4 clock periods.

Formula:
Word Count Register = N - 1
T_DMA_cycle = 4 / f_clock
T_total = N x T_DMA_cycle

Substitution:
Word Count Register = 512 - 1 = 511 = 01FFh
T_DMA_cycle = 4 / 5,000,000 = 0.8 microseconds
T_total = 512 x 0.8 us

Calculation:
T_total = 409.6 microseconds

Final Answer:
Load 01FFh into word count register. Transfer completes in 409.6 microseconds.

Exam Tip: Always remember that the 8237 word count register is loaded with N-1 for N bytes. In GATE problems, TC is generated when the count rolls from 0000h to FFFFh, not when it reaches zero. Cascade mode does not perform any data transfer itself; it only connects HRQ/HLDA of the slave to the master channel.

Practical Understanding

In early PC architectures, Channel 0 of the 8237 was used for DRAM refresh (triggered periodically), Channel 1 for SDLC serial transfers, Channel 2 for floppy disk, and Channel 3 for hard disk. Modern systems use bus mastering DMA built into PCI/PCIe devices, but the 8237 model remains the foundation for understanding DMA handshake sequences, bus arbitration, and transfer modes in exam contexts.

The distinction between HRQ and HLDA handshake is analogous to requesting and granting access to a shared resource. The CPU relinquishes the bus only after completing the current cycle to maintain bus coherency, which is an important concept in bus arbitration and multimaster system design.

Mechanism: DMA Transfer Sequence

• Step 1: CPU programs 8237 with source/destination address, word count, transfer mode, and transfer type via I/O write cycles.
• Step 2: When peripheral has data ready, it asserts DREQ to the 8237. The 8237 checks if the channel is masked; if not, it asserts HRQ to the CPU.
• Step 3: CPU completes its current bus cycle, floats address/data/control buses, and asserts HLDA to acknowledge the hold request.
• Step 4: 8237 takes control of the address bus, drives the target memory address from its Current Address Register, and asserts DACK to the peripheral.
• Step 5: Data is transferred directly between peripheral and memory. After each byte, the address register increments and word count decrements.
• Step 6: When word count reaches FFFFh (terminal count), TC is asserted, DACK is removed, HRQ is de-asserted, and CPU resumes control of the bus.

Quick Revision

• 8237 has 4 DMA channels, each with base and current address and word count registers.
• Word count register = N-1 for N bytes transfer. TC fires when count rolls from 0000h to FFFFh.
• Transfer modes: Single (one byte per DREQ), Block (hold bus entire transfer), Demand (hold while DREQ active), Cascade (for expanding channels).
• Bus handshake: DREQ in, DACK out (peripheral side); HRQ out, HLDA in (CPU side).
• Auto-initialize: reloads base registers into current registers after TC for continuous DMA operation.
• Memory-to-memory transfer uses Ch0 (source) and Ch1 (destination) together.
• Exam trap: Cascade mode does not transfer data; it only routes HRQ/HLDA from slave to master 8237.