8085 Architecture Overview

The Intel 8085 is an 8-bit microprocessor that forms the backbone of undergraduate microprocessor courses and appears consistently in GATE examinations. Understanding its internal architecture is not merely about memorizing block names. It requires grasping how the arithmetic unit, register file, control logic, and bus interface interact during instruction execution. A clear architectural understanding also prepares students for timing diagrams, interrupt handling, and assembly language programming that follow in subsequent topics.

Core Concept Explanation

The 8085 is an 8-bit microprocessor meaning its data bus, arithmetic unit, and general-purpose registers all handle 8 bits at a time. However, it has a 16-bit address bus, allowing it to address up to 65536 (64K) memory locations. This asymmetry is a fundamental design choice: data operations are byte-wide for simplicity and cost, while the address space is larger to support meaningful programs and data storage.

The Arithmetic Logic Unit (ALU) is the computational core. It performs all arithmetic operations such as addition and subtraction, and all logical operations such as AND, OR, XOR, and rotate. The ALU always uses the Accumulator register (A) as one operand and stores the result back into the Accumulator. This accumulator-based architecture is simpler to design but requires more instructions compared to general-purpose register architectures like modern CPUs.

The register file contains six 8-bit general-purpose registers: B, C, D, E, H, and L. These can be used individually for 8-bit operations or paired as BC, DE, and HL for 16-bit address and data operations. The HL pair is especially important because it functions as a memory pointer: the M operand in 8085 instructions refers to the memory location whose address is held in the HL register pair. This indirect addressing through HL is used extensively in loops and array processing.

The Program Counter (PC) is a 16-bit register that always holds the address of the next instruction to be fetched from memory. After each fetch, the PC is automatically incremented. The Stack Pointer (SP) is another 16-bit register pointing to the top of the stack in memory. During CALL and PUSH instructions, the SP decrements and data is stored; during RET and POP, the SP increments and data is retrieved. The stack grows downward in memory.

Flags and ALU Status

The 8085 has a dedicated flags register with five active flag bits. The Sign flag (S) is set if the result is negative (MSB equals 1). The Zero flag (Z) is set if the result is zero. The Auxiliary Carry (AC) flag is set if there is a carry from bit 3 to bit 4, used specifically for BCD arithmetic operations. The Parity flag (P) is set if the result has even parity. The Carry flag (CY) is set if there is a carry out from the MSB during addition or a borrow during subtraction.

Flags are automatically updated after most ALU operations and are used by conditional branch instructions such as JZ, JNZ, JC, JNC, JP, JM, JPE, and JPO. The flags register together with the Accumulator forms the Program Status Word (PSW), which can be pushed onto the stack as a 16-bit unit to save the CPU state during interrupts or subroutine calls.

Instruction Fetch and Decode Mechanism

When the 8085 fetches an instruction, it places the PC value on the address bus and asserts the RD (Read) control signal. The memory responds by placing the opcode byte on the data bus. The 8085 latches this byte into the Instruction Register (IR). The Instruction Decoder then interprets the opcode and generates the sequence of internal control signals required to execute that instruction. For multi-byte instructions, subsequent machine cycles fetch the operand bytes.

The Timing and Control Unit generates all external control signals including ALE (Address Latch Enable), RD (Read), WR (Write), and IO/M (to distinguish between memory and I/O access). The ALE signal is active during the first clock state of each machine cycle to indicate that the AD0-AD7 bus currently carries address information, which must be externally latched because these lines are multiplexed for data in subsequent states.

Numerical Example

A common GATE-style problem involves calculating how many machine cycles and T-states a given instruction requires, and then computing execution time. Consider the LDA instruction, which loads the Accumulator from a direct memory address. This is a 3-byte, 4-machine-cycle instruction requiring 13 T-states total.

Given:
Instruction: LDA (Load Accumulator direct, 3-byte instruction)
Clock frequency: f = 2 MHz
T-state duration = 1/f

Why this formula applies:
Execution time = Total T-states × T-state duration
LDA requires: OF(4T) + RD addr-low(3T) + RD addr-high(3T) + RD memory(3T) = 13 T-states

Formula:
T-state duration = 1 / f
Execution time = N_T × (1/f)

Substitution:
T-state duration = 1 / (2 × 10⁶) = 0.5 µs
Execution time = 13 × 0.5 µs

Calculation:
Execution time = 6.5 µs

Final Answer:
LDA executes in 13 T-states = 6.5 µs at 2 MHz clock
Machine cycles: 4 (Opcode Fetch + 2 Memory Read for address bytes + 1 Memory Read for data)

Exam Tip: GATE frequently asks about PSW (Program Status Word) = Accumulator + Flags Register pushed as 16-bit pair. Also remember: the 8085 has 5 flags (S, Z, AC, P, CY), NOT 8. The D1 and D5 positions in the flags register are always 0 and 1 respectively — a common trap in multiple-choice questions.

Quick Revision

• 8085 is an 8-bit microprocessor with a 16-bit address bus. It can address 64KB (2^16 = 65536 locations) of memory.
• ALU operates only on the Accumulator (A register) as destination. Results always go back to A. General-purpose registers B,C,D,E,H,L can be paired as BC, DE, HL for 16-bit operations.
• Five active flags: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), Carry (CY). PSW = A + Flags as 16-bit pair.
• HL register pair acts as memory data pointer. M in instructions means memory location addressed by HL.
• Stack Pointer (SP) points to top of stack in RAM. Stack grows downward. PUSH decrements SP, POP increments SP.
• ALE signal is generated during T1 of every machine cycle to indicate that AD0-AD7 carries a valid address (must be latched externally using 8212 or 74LS373).
• Maximum clock frequency of 8085 is 3 MHz (original). Execution time = T-states / clock frequency. LDA = 13 T-states, MOV r,r = 4 T-states.