7 Segment Display Interface

A 7-segment display is a simple output device consisting of seven LED segments (labeled a through g) arranged to display decimal digits and a few alphabetic characters. When interfaced to a microprocessor system using the 8255 Programmable Peripheral Interface, multiple display units can be driven using a technique called multiplexing, which reduces the number of output port lines required and is a fundamental I/O interfacing concept in embedded system design.

Core Concept Explanation

A 7-segment display has 8 connections: segments a, b, c, d, e, f, g, and the decimal point (dp). To display a digit, the appropriate segments are turned ON. For example, to display 0, segments a, b, c, d, e, f are lit and g is off. If 4 displays are directly driven, the CPU would need 4 x 8 = 32 output lines. Multiplexing reduces this to 8 segment lines (shared) plus one select line per digit.

In multiplexed operation, only one digit is physically energized at any given instant. The 8255 Port A outputs the segment code for the active digit, while Port B enables the corresponding digit via a transistor switch. The CPU rapidly cycles through all digits in sequence, enabling each for a short time (typically 1 to 5 ms). Due to persistence of vision, the human eye perceives all digits as simultaneously lit, provided the refresh rate is above approximately 50 Hz per digit.

The 8255 is programmed in Mode 0 (Basic I/O) for this application. Port A is configured as output for segment data and Port B as output for digit selection. The control word for both ports as output is calculated and written to the 8255 control register at the initialization stage.

Segment Encoding Table

Each digit corresponds to a unique 8-bit pattern where each bit controls one segment. For a common cathode display, a segment lights when its bit is HIGH (1). The standard segment code for digit 0 through 9 in the bit order dp-g-f-e-d-c-b-a is: 0=3Fh, 1=06h, 2=5Bh, 3=4Fh, 4=66h, 5=6Dh, 6=7Dh, 7=07h, 8=7Fh, 9=6Fh.

Mathematical Expression

The minimum refresh rate for flicker-free display must ensure each digit is enabled at least 50 times per second. For N digits, the total cycle time must be at most 1/50 = 20 ms. Therefore, the maximum ON time per digit is 20 ms / N. For 4 digits, each digit gets a maximum of 5 ms ON time. In practice, a software delay of 2 to 3 ms is used per digit to maintain reasonable brightness.

The 8255 control word for Mode 0, all ports as output: D7=1 (mode set), D6D5=00 (Port A Mode 0), D4=0 (Port A output), D3=0 (Port C upper output), D2=00 (Port B Mode 0), D1=0 (Port B output), D0=0 (Port C lower output). Control word = 1000 0000 = 80h.

Given:
Number of digits = 4
Desired refresh rate = 100 Hz (each digit appears 100 times/sec)
Port A = segment data, Port B = digit select

Why this formula applies:
For N digits at refresh rate f, ON-time per digit = 1/(N x f)

Formula:
ON-time per digit = 1 / (N x f_refresh)

Substitution:
ON-time = 1 / (4 x 100)

Calculation:
ON-time = 1/400 = 2.5 ms per digit

Final Answer:
Each digit must be enabled for 2.5 ms in the multiplexing loop.
8255 control word (Mode 0, all output) = 80h
Digit select for digit 1 (Port B): 01h, digit 2: 02h, digit 3: 04h, digit 4: 08h

Exam Tip: The 8255 control word for Mode 0 with all ports as output is 80h. For common cathode displays, segment is ON when bit is HIGH. For common anode displays, segment is ON when bit is LOW (inverted codes). Multiplexing refresh rate below 50 Hz per digit causes visible flicker. Always check whether the problem specifies common cathode or common anode before writing segment codes.

Practical Understanding

In practice, segment lines carry current for all digits' segments simultaneously (just different patterns over time), while transistors on the digit select lines switch the common cathode (or anode) of each display unit. NPN transistors (BC547) or Darlington arrays (ULN2003) are used on digit select lines because 8255 output current is typically limited to 2.5 mA, insufficient to drive multiple LED segments directly at full brightness.

For large displays (more than 6 digits), a dedicated display controller IC or a dedicated microcontroller PWM peripheral replaces software multiplexing, since tight timing requirements become difficult to meet if the CPU is also handling interrupts and other tasks.

Mechanism: Multiplexing Sequence

• The software loop outputs the segment pattern for digit 1 to Port A, then enables digit 1 by asserting PB0 HIGH, waits for the slot duration, then de-selects it.
• The loop then repeats for digit 2 (PB1), digit 3 (PB2), and digit 4 (PB3) in sequence, creating a continuous rotating scan.
• Only one digit is physically conducting current at a time, reducing average current and total power consumption compared to static multiplexing.
• The transistor switch on each digit select line amplifies the Port B output current to adequately drive the common cathode of each display at sufficient brightness.
• Increasing the slot duration increases brightness but reduces refresh rate. A balance between brightness and flicker-free operation is maintained at 2 to 5 ms per digit.

Quick Revision

• 7-segment display: 7 segments a-g plus dp. Common cathode: segment ON when bit = 1. Common anode: segment ON when bit = 0.
• Multiplexing: shared segment bus (Port A), individual digit select (Port B). One digit active at a time.
• 8255 control word for Mode 0, all ports output = 80h.
• Minimum refresh rate = 50 Hz per digit. ON-time per digit = 1 / (N x f_refresh).
• Segment codes (common cathode, dp=0): 0=3Fh, 1=06h, 2=5Bh, 3=4Fh, 4=66h, 5=6Dh, 6=7Dh, 7=07h, 8=7Fh, 9=6Fh.
• Exam trap: Writing segment pattern and enabling wrong digit simultaneously causes ghost digits. Always output segment code before asserting digit select.