Timing Diagrams

Every instruction executed by the 8085 microprocessor consumes a precise number of clock cycles, organized into a strict hierarchy of timing units. Understanding timing diagrams allows engineers and students to analyze how the 8085 interacts with memory and I/O devices at the signal level, diagnose interface timing violations, and answer quantitative GATE questions about instruction execution times. The three key levels of this hierarchy are the T-state, the machine cycle, and the instruction cycle.

Core Concept Explanation

The smallest unit of time in the 8085 timing system is the T-state (clock state). Each T-state lasts exactly one clock period, equal to 1/f where f is the operating clock frequency. The 8085 cannot perform a faster operation than one T-state. Internal operations such as incrementing the PC, latching data, or performing an ALU computation each take one T-state.

A machine cycle is a group of T-states that accomplishes one specific bus operation. The 8085 defines five types of machine cycles: Opcode Fetch (OF), Memory Read (MR), Memory Write (MW), I/O Read (IOR), and I/O Write (IOW). Each machine cycle begins with ALE going high in T1 and proceeds through T2 and T3 for the bus transfer. Some machine cycles include a T4 state for internal processing. If the READY signal is low during T2, additional wait states (TW, each one clock period) are inserted between T2 and T3.

An instruction cycle is the complete sequence of machine cycles required to fetch and execute one instruction. Different instructions have different instruction cycles because they require different numbers of bus accesses. A simple register-to-register MOV instruction takes only one machine cycle (opcode fetch, 4 T-states total). The LDA instruction, which loads the accumulator from a 16-bit direct address, requires 4 machine cycles (1 opcode fetch + 2 memory reads for the address bytes + 1 memory read for the actual data), totaling 13 T-states.

Opcode Fetch Machine Cycle Details

The Opcode Fetch is the first machine cycle of every instruction and always takes 4 T-states. During T1, the 8085 places the PC value on the address bus, asserts ALE high, and the AD0-AD7 lines carry the lower 8 bits of the PC. An external latch captures A0-A7. During T2, ALE falls, RD is asserted low, and the AD bus transitions to receive data (the opcode byte). During T3, the memory must have placed the opcode on the data bus; the 8085 samples the data. During T4, the 8085 decodes the opcode and determines how many additional machine cycles are needed. This decode step in T4 is what distinguishes the opcode fetch from a regular memory read cycle, which typically uses only 3 T-states.

The memory read cycle (for operand bytes or data) follows the same T1/T2/T3 pattern but has no T4 decode state, giving it 3 T-states. The memory write cycle similarly uses 3 T-states. The I/O read and I/O write cycles each use 3 T-states but with IO/M held high to distinguish I/O from memory access.

Mathematical Expression

The total execution time for any instruction is calculated as: execution time equals the total number of T-states multiplied by the T-state duration (1/f). For a program with multiple instructions, the total execution time is the sum of execution times of all instructions. The T-state count for common instructions must be memorized for GATE: MOV r,r = 4T, MOV r,M = 7T, MVI r = 7T, ADD r = 4T, LDA = 13T, STA = 13T, CALL = 18T, RET = 10T.

Numerical Example

Consider a small program segment and compute total execution time at a given clock frequency. This type of problem is directly asked in GATE and university examinations, requiring knowledge of T-state counts per instruction.

Given:
Clock frequency: f = 2 MHz
Program segment:
  LDA 2050H   ; 13 T-states
  MOV B, A    ; 4 T-states
  ADD B       ; 4 T-states
  STA 3050H   ; 13 T-states

Why this formula applies:
Total T-states = sum of T-states for each instruction
Execution time = Total T-states / f

Formula:
T_total = ΣT_i
Execution time = T_total × (1/f)

Substitution:
T_total = 13 + 4 + 4 + 13 = 34 T-states
T-state duration = 1 / (2 × 10⁶) = 0.5 µs

Calculation:
Execution time = 34 × 0.5 µs = 17 µs

Final Answer:
Total T-states = 34
Execution time = 17 µs at 2 MHz clock

Exam Tip: GATE often gives a clock frequency and asks execution time for a mix of instructions. Always count T-states per instruction (not machine cycles). Remember: Opcode Fetch = 4T, Memory Read/Write = 3T each, I/O Read/Write = 3T each, Wait state TW = 1T per READY assertion missed. CALL instruction = 18T = OF(4) + 2 extra reads + stack write cycles.

T-state Counting Details

• The Opcode Fetch machine cycle always uses 4 T-states (T1 through T4). The extra T4 is needed for internal opcode decoding. All other machine cycles use 3 T-states minimum.
• Wait states (TW) are inserted between T2 and T3 whenever READY is sampled low at the falling edge of T2. Each wait state adds one full clock period to the machine cycle, allowing slow memory or peripherals extra time to respond.
• The HLT instruction causes the 8085 to tri-state the address and data buses after completing the opcode fetch. The processor remains halted until an interrupt or RESET is received.
• The CALL instruction pushes the return address (PC+3) onto the stack, requiring two Memory Write machine cycles in addition to the opcode fetch and two operand reads. This accounts for its 18 T-state count.
• For IN and OUT instructions, the 8-bit port address appears on both A0-A7 and A8-A15 during the I/O machine cycle. The IO/M pin is high to indicate an I/O operation rather than memory access.

Quick Revision

• T-state = 1 clock period = 1/f seconds. Machine cycle = group of T-states for one bus operation. Instruction cycle = all machine cycles for one instruction.
• Opcode Fetch = always 4 T-states (T1 to T4). Memory Read = 3T. Memory Write = 3T. I/O Read = 3T. I/O Write = 3T.
• Key T-state counts: MOV r,r = 4T, MOV r,M = 7T, MVI r = 7T, LDA = 13T, STA = 13T, CALL = 18T, RET = 10T, IN/OUT = 10T.
• Wait states are inserted when READY = 0 at T2. Each wait state = 1T. Formula: effective machine cycle time = (3 + Nw) × T, where Nw is number of wait states.
• Execution time formula: t = (total T-states) / f. For a program, sum T-states of all instructions, then divide by clock frequency.
• Common trap: GATE may give number of machine cycles and ask T-states, or vice versa. Know both counts per instruction, not just one.