8086 Pin Diagram

The 8086 microprocessor is a 16-bit CPU developed by Intel, and understanding its pin diagram is fundamental to interfacing it with memory, I/O devices, and support chips. Each pin serves a specific role in controlling data flow, address generation, and system synchronization. GATE and university exams consistently test pin functions, especially those that change behavior between minimum and maximum modes.

Pin Groups and Their Functions

The 8086 has 40 pins organized into functional groups. The address/data bus (AD0-AD15) is multiplexed, meaning the same pins carry 16-bit address information during the first clock cycle (T1) and 16-bit data in subsequent cycles. The upper four address lines A16-A19 are multiplexed with status signals S3-S6, providing the full 20-bit address space of 1 MB.

The MN/MX pin (pin 33) determines the operating mode of the processor. When tied to Vcc, the 8086 runs in minimum mode, where it generates all control signals itself. When tied to GND, it operates in maximum mode, offloading bus control to an external bus controller chip (8288). This distinction is heavily tested in exams.

The READY pin is used by slow memory or I/O devices to insert wait states into the bus cycle. When READY is low, the processor inserts T-wait states between T3 and T4 of the bus cycle, effectively pausing until the device is ready to transfer data. This mechanism allows the 8086 to interface with devices of varying speeds.

Key Control Pins

The LOCK pin is an output in maximum mode that signals other bus masters not to use the system bus. It is activated by prefixing an instruction with the LOCK prefix. This is critical in multiprocessor systems where shared resources must be accessed atomically.

The BHE (Bus High Enable) signal, combined with A0, controls which byte of the 16-bit data bus is active during a memory access. BHE=0 and A0=0 selects the full 16-bit word. BHE=0 and A0=1 selects the upper byte (D8-D15) only. A0=0 and BHE=1 selects the lower byte (D0-D7). This byte-enable mechanism allows 8086 to address odd and even memory banks separately.

Interrupt pins include INTR (maskable interrupt) and NMI (non-maskable interrupt). INTR can be disabled by clearing the Interrupt Flag (IF), whereas NMI cannot be masked. RESET causes the processor to initialize its registers and start execution from address FFFF0H.

Minimum vs Maximum Mode Pin Differences

Pins 24-31 have dual definitions depending on the MN/MX pin state. In minimum mode, these pins generate control signals such as M/IO (memory or I/O select), WR (write), INTA (interrupt acknowledge), ALE (address latch enable), DEN (data enable), DT/R (data transmit/receive), and HLDA (hold acknowledge). In maximum mode, these same pins output encoded status signals (S0, S1, S2) and queue status (QS0, QS1) for use by the 8288 bus controller.

Numerical Example

The 8086 uses a 20-bit address bus to generate physical addresses. The physical address is formed from a segment register and an offset register. The formula is: Physical Address = Segment x 16 + Offset. Since multiplying by 16 is equivalent to shifting left by 4 bits, the segment register value occupies bits 19-4 and the offset adds to the lower 16 bits.

Given:
Segment Register (CS) = 1234H
Instruction Pointer (IP) = 0056H

Why this formula applies:
The 8086 generates a 20-bit physical address by shifting the segment left 4 bits and adding the offset.

Formula:
Physical Address = (Segment x 16) + Offset

Substitution:
Physical Address = (1234H x 10H) + 0056H
= 12340H + 0056H

Calculation:
12340H + 0056H = 12396H

Final Answer: Physical Address = 12396H (= 74,646 in decimal)

Exam Tip: In GATE questions, MN/MX = Vcc means minimum mode (8086 generates its own control signals). MN/MX = GND means maximum mode (8288 bus controller is used). Never confuse the two. Also remember BHE and A0 together select word, high byte, or low byte.

Mechanism: Address Latching and Bus Cycle

• AD0-AD15 carry address in T1 and data in T3/T4 of each bus cycle.
• ALE goes high during T1 to tell the external 8282 latch to capture the address before the bus switches to data mode.
• READY pin allows slow memory to insert wait states (Tw) between T3 and T4.
• MN/MX pin is tied at hardware design time and determines whether 8086 or 8288 generates bus control signals.
• LOCK prefix activates the LOCK pin, preventing other bus masters from accessing the bus during a critical instruction sequence.

Quick Revision

• 8086 is a 40-pin DIP IC with 20-bit address bus giving 1 MB addressable memory.
• AD0-AD15 are multiplexed: address in T1, data in T3-T4. ALE latches the address externally.
• MN/MX = Vcc is minimum mode; MN/MX = GND is maximum mode (requires 8288 bus controller).
• Physical Address = Segment x 10H + Offset (20-bit result).
• READY = LOW inserts wait states. INTR is maskable; NMI is not maskable.
• BHE and A0 together select word (00), high byte (01), or low byte (10) access.
• LOCK pin (max mode) prevents bus access by other masters during atomic instruction sequences.