Time Delay Loops

In 8085 microprocessor programming, generating precise time delays is a fundamental requirement for applications like traffic light control, serial communication timing, and LCD refresh rates. Time delay loops are written using counting registers and conditional jump instructions, where the delay duration is calculated precisely from the clock frequency and T-state count of each instruction.

Core Concept: What is a Time Delay Loop

A time delay loop in 8085 assembly is a program segment that consumes a known number of processor clock cycles without performing any useful computation, simply to introduce a precise time gap. The processor executes each instruction in a fixed number of T-states (clock cycles). By counting the total T-states consumed by the loop body multiplied by the number of iterations, the total time elapsed can be calculated from the clock frequency.

The basic single-loop delay structure uses one register loaded with a count value N. Inside the loop, DCR (Decrement Register) decreases the count by 1, and JNZ (Jump if Not Zero) sends control back to the top of the loop if the register is not yet zero. The loop body executes exactly N times before falling through.

The critical detail is that JNZ takes 10 T-states when the jump is taken (all iterations except the last) and only 7 T-states when the jump is not taken (the final iteration when register becomes zero). DCR takes 4 T-states. This asymmetry must be accounted for in accurate delay calculations.

Mathematical Expression: Delay Calculation

For a single loop using registers, the total T-states consumed can be expressed as follows. The initialization instruction MVI R, N takes 7 T-states and executes once. The loop body (DCR + JNZ taken) executes N minus 1 times at 14 T-states each. The final iteration (DCR + JNZ not taken) executes once at 11 T-states.

The simplified formula for total T-states is: T_total = 7 + (N-1) x 14 + 11 = 7 + 14N - 14 + 11 = 14N + 4. The actual time delay is then: Delay = T_total x T_clock = T_total / f_clock where f_clock is the operating frequency of the 8085 system.

For the 8085, the typical operating frequency used in GATE problems is 2 MHz or 3 MHz. At 2 MHz, each T-state is 0.5 microseconds. At 3 MHz, each T-state is approximately 0.333 microseconds.

Practical Understanding: Nested Loops and Longer Delays

A single 8-bit register can count from 00H to FFH (0 to 255), giving a maximum loop count of 256 (when initialized with 00H, the DCR makes it FFH on first decrement, effectively giving 256 iterations). For a 2 MHz clock, this gives approximately 256 x 14 x 0.5 µs = 1.792 milliseconds as the maximum single-loop delay.

For longer delays, nested loops are used with two registers, an outer counter and an inner counter. The inner loop runs to completion for each decrement of the outer loop. Total iterations become the product of both counters. For a 16-bit delay counter, the BC or DE register pair can be used with DCX and a zero-check using MOV A,B followed by ORA C and JNZ.

Nested loops introduce additional overhead instructions in the outer loop body, so the T-state count per outer iteration includes the cost of reinitializing the inner counter. Each such overhead instruction adds to the total T-states and must be included in an accurate delay calculation.

Given:
8085 operating frequency = 2 MHz (T_clock = 0.5 µs)
Delay loop: MVI C, 64H followed by DCR C and JNZ LOOP
Count loaded = 64H = 100 decimal

Why this formula applies:
Each loop iteration consumes fixed T-states; total delay = T_total x T_clock

Formula:
T_total = 7 (MVI) + (N-1) x 14 (taken JNZ iterations) + 11 (last iteration)
T_total = 14N + 4

Substitution:
N = 100
T_total = 14 x 100 + 4 = 1404 T-states

Calculation:
Delay = 1404 x 0.5 µs = 702 µs

Final Answer with units:
Delay = 702 microseconds for N = 100 at 2 MHz clock frequency.

Exam Tip: In GATE problems, JNZ takes 10 T-states when jump is taken and 7 when not taken. Most students use 10 for all N iterations, which overestimates the delay by 3 T-states. Always subtract 3 from the JNZ count once for the last iteration. For large N, this difference is small but conceptually important.

How the Loop Executes: Step-by-Step

• MVI C, N loads the delay count into register C (7 T-states, executed once outside the loop).
• DCR C decrements register C by 1 and sets the Zero flag if C becomes 0 (4 T-states per iteration).
• JNZ LOOP jumps back to DCR C if Zero flag is not set, consuming 10 T-states; on the last iteration (C = 0), no jump occurs, consuming 7 T-states.
• Total loop body cost per taken iteration: 4 + 10 = 14 T-states; final iteration: 4 + 7 = 11 T-states.
• For a 16-bit nested delay, DCX does not affect flags; MOV A,B then ORA C checks if BC = 0000H (each check adds extra T-states to the inner overhead).

Quick Revision

• Time delay = T_total T-states x (1 / clock frequency).
• Single loop formula: T_total = 14N + 4, where N is the initial count.
• DCR = 4 T-states, JNZ (taken) = 10 T-states, JNZ (not taken, last iter) = 7 T-states.
• MVI R, N = 7 T-states, executes once at loop start.
• Maximum single-register delay count = 256 (MVI C, 00H causes 256 decrements).
• Nested loops multiply iteration counts; add overhead of outer loop body T-states.
• Trap: DCX (decrement register pair) does not set Zero flag; use MOV+ORA to detect zero for 16-bit loops.