Instruction Set Groups

The 8085 microprocessor supports 74 unique instructions, each belonging to one of five functional groups. These groups are Data Transfer, Arithmetic, Logical, Branching, and Machine Control. Classifying instructions by group helps understand their purpose, their effect on flags, and their typical use in programs. GATE questions frequently test which instructions affect which flags, and that distinction flows directly from group classification.

Group 1: Data Transfer Instructions

Data transfer instructions move data between registers, between registers and memory, or load immediate values. They do not perform any computation and, critically, they do not affect any flags in the flag register. This group includes MOV (register to register), MVI (immediate to register), LDA (load accumulator from direct address), STA (store accumulator), LHLD, SHLD (16-bit load/store), LDAX, STAX (load/store using register pair), and XCHG (exchange HL and DE pairs).

A common exam trap is assuming MOV or LDA will change the Zero or Sign flag. They do not. Only the value in the destination register changes; all five flags (Sign, Zero, Auxiliary Carry, Parity, Carry) remain exactly as they were before the instruction executed.

Group 2: Arithmetic Instructions

Arithmetic instructions perform addition, subtraction, increment, and decrement operations. Most of them affect all five flags: S (sign), Z (zero), AC (auxiliary carry), P (parity), and CY (carry). The most used instructions are ADD (add register to A), ADI (add immediate to A), ADC (add with carry), SUB, SUI, SBB, INR (increment register by 1), DCR (decrement register by 1), DAD (double add: adds a 16-bit register pair to HL), INX (increment register pair), and DCX (decrement register pair).

Two critical exceptions that appear repeatedly in GATE: INX and DCX operate on 16-bit register pairs and do not affect any flags at all. DAD (which adds a 16-bit pair to HL) affects only the Carry flag (CY) and no other flags. These exceptions are tested almost every year.

Group 3: Logical Instructions

Logical instructions perform bitwise AND, OR, XOR, compare, complement, and rotate operations. The standard logical operations ANA (AND), ORA (OR), XRA (XOR) affect S, Z, AC, P flags and always clear the Carry flag (CY = 0) after execution. This clearing of carry is another high-frequency exam point.

The CMP instruction (compare register with accumulator) performs an internal subtraction of the register from A but does not store the result back into A. It only sets the flags based on the result. This is used to make conditional branching decisions. The rotate instructions RLC, RRC, RAL, RAR affect only the Carry flag and no other flags.

Group 4: Branching Instructions

Branching instructions alter the flow of program execution by loading a new value into the Program Counter. Unconditional branches are JMP (jump), CALL (call subroutine), and RET (return from subroutine). Conditional branches check a specific flag and branch only if the condition is met. Examples include JZ (jump if zero flag set), JNZ (jump if zero flag clear), JC (jump if carry set), JNC (jump if carry clear), JM (jump if sign negative), JP (jump if positive), JPE (jump if parity even), JPO (jump if parity odd).

Conditional CALL and RET instructions (CZ, CNZ, CC, CNC, etc.) also exist. Branching instructions themselves do not modify any flags; they only read them. CALL pushes the return address onto the stack; RET pops it back.

Group 5: Machine Control Instructions

Machine control instructions manage the overall operating state of the processor. NOP (no operation) wastes one machine cycle without doing anything useful, often used for timing delays. HLT stops the CPU until a reset or interrupt. EI (enable interrupts) and DI (disable interrupts) control the interrupt system. RIM (read interrupt mask) and SIM (set interrupt mask) handle interrupt masking and serial I/O configuration. These instructions generally do not affect arithmetic flags.

Flag Behavior: The Critical Distinguisher

The five 8085 flags are stored in the Flag Register (F), which is an 8-bit register where only bits 7 (S), 6 (Z), 4 (AC), 2 (P), and 0 (CY) are used. Understanding which group and which specific instruction affects which flag is more important for GATE than memorizing all 74 instructions individually. The core rule is: Data Transfer = no flags, Arithmetic = all flags (with INX/DCX/DAD exceptions), Logical AND/OR/XOR = all flags with CY always cleared, CMP = all flags (but A unchanged), Rotate = only CY.

Given:
  Register B = 85H = 1000 0101b
  Accumulator A = 85H
  Instruction: ANA B (Logical AND of A with B)

Why this formula applies:
  ANA performs bitwise AND. It clears CY, clears AC (or sets based on bit 3), sets S, Z, P based on result.

Formula:
  Result = A AND B (bitwise)
  CY = 0 (always after ANA)
  S = bit 7 of result
  Z = 1 if result = 0, else 0
  P = 1 if number of 1s in result is even

Substitution:
  A = 1000 0101b
  B = 1000 0101b
  Result = 1000 0101b AND 1000 0101b = 1000 0101b = 85H

Calculation:
  Result = 85H (nonzero)
  S = 1 (bit 7 is 1, negative)
  Z = 0 (result not zero)
  CY = 0 (always cleared by ANA)
  P = parity of 85H = 1000 0101 → three 1s → odd → P = 0

Final Answer:
  A = 85H, S=1, Z=0, CY=0, P=0 after ANA B with A=B=85H.

Exam Tip: INX and DCX never affect any flags. DAD affects only CY. ANA/ORA/XRA always clear CY. CMP sets flags like SUB but does not change the accumulator. These four rules eliminate most flag-related GATE errors.

Quick Revision

• Five groups: Data Transfer (no flags), Arithmetic (all flags), Logical (all flags, CY cleared by AND/OR/XOR), Branching (reads flags, changes PC), Machine Control (minimal flags).
• INX, DCX: 16-bit increment/decrement, affect NO flags.
• DAD: 16-bit addition to HL, affects ONLY CY flag.
• CMP: internal subtraction, sets all flags, but A is unchanged.
• ANA, ORA, XRA: always set CY = 0 after execution.
• Rotate instructions (RLC, RRC, RAL, RAR): affect only CY (and the bit rotated into carry).
• Exam trap: MOV, LDA, STA, XCHG do not affect any flags whatsoever.