Memory Interfacing

The 8086 microprocessor cannot operate in isolation. It requires external memory interfacing to store programs and data. Connecting EPROM and RAM chips to the 8086 bus system involves careful address decoding so that each chip responds only to its assigned address range. Understanding this topic is essential for designing real microprocessor systems and is a recurring area in GATE questions.

Core Concept Explanation

The 8086 has a 20-bit address bus, giving it the ability to address 2^20 = 1,048,576 unique byte locations, which is 1 MB of memory space. This 1 MB space runs from address 00000H to FFFFFH. In a real system, this space is divided among different memory chips. Each chip occupies a specific range of this address space. The process of assigning address ranges to chips and generating chip select (CS) signals for each chip is called address decoding.

The 8086 address bus has 20 lines: A0 through A19. When the CPU wants to access memory, it places the 20-bit address of the target location on these lines. The address decoder examines the higher-order address bits (typically A19 down to A12 or so) to determine which chip should respond. The lower-order bits (A11 down to A0 for a 4 KB chip, for example) are connected directly to the address pins of the selected chip to identify the specific location within that chip.

Two types of memory chips are used in 8086 systems. EPROM (Erasable Programmable Read-Only Memory) stores the system firmware or program code permanently. It is a read-only device during normal operation. SRAM or DRAM provides read/write memory for temporary data storage, stack operations, and variable storage. Both types of chips have Chip Enable (CE) or Chip Select (CS) pins that must be asserted (usually active low) for the chip to respond to bus transactions.

Address Decoding

Address decoding can be implemented in three ways. In full address decoding, all address lines are used in the decoding logic. Each memory location maps to exactly one physical address. There is no aliasing. This is the most reliable approach but requires more hardware.

In partial address decoding, only some of the higher address bits are used. This reduces hardware but causes aliasing, where one physical memory location responds to multiple address values. For example, if A19 alone is used to select a chip, the chip responds to all addresses with A19 = 0, which is a 512 KB range rather than just the chip's actual capacity.

The 74LS138 is a commonly used 3-to-8 line decoder IC in 8086 systems. It takes three address lines as input and generates eight active-low chip select outputs. Combined with enable inputs controlled by other address lines, it can decode address ranges efficiently for multiple chips.

Mathematical Expression

The size of the address range assigned to a memory chip depends on how many address lines of the chip are connected to the bus. If a chip has N address pins, it can store 2^N bytes. The number of higher-order address bits used for decoding equals 20 minus N for a byte-addressable system. For example, an 8 KB EPROM has 13 address pins (A0 to A12, since 2^13 = 8192), so 20 minus 13 = 7 higher bits are available for decoding.

Practical Understanding

In a typical 8086 system, EPROM is placed at the top of the address map (near FFFFFH) because the 8086 fetches its first instruction from address FFFF0H after reset. RAM is usually placed at lower addresses where programs store runtime data and the stack. This physical arrangement is implemented by the address decoder.

The 8086 data bus is 16 bits wide. Memory is organized as two banks: a low bank (even addresses, connected to D7-D0) and a high bank (odd addresses, connected to D15-D8). The BHE (Bus High Enable) signal along with A0 is used to select which bank or both banks participate in a memory transfer. This byte-enable mechanism is important when connecting 8-bit memory chips to the 16-bit 8086 data bus.

Solved Example

A 4 KB EPROM is to be interfaced with the 8086 at the address range 00000H to 00FFFH. Determine the address lines used for decoding and the chip's internal address lines.

Given:
EPROM size = 4 KB = 4096 bytes = 2^12 bytes
Target address range: 00000H to 00FFFH
20-bit address bus (A19 to A0)

Why this formula applies:
Number of chip address pins = log2(chip size in bytes)
Remaining higher bits = 20 - number of chip pins (used for decoding)

Formula:
Chip address pins = log2(4096) = 12 pins (A11 to A0)
Decoding bits = 20 - 12 = 8 bits (A19 to A12)

Substitution:
For range 00000H to 00FFFH:
A19 A18 A17 A16 A15 A14 A13 A12 = 0 0 0 0 0 0 0 0
All 8 higher bits must be 0 to select this EPROM.

Calculation:
Chip select logic: CS = A19 NOR A18 NOR ... NOR A12
(Active when all 8 bits are zero)
A11 to A0 connect to the EPROM's 12 internal address pins.

Final Answer:
EPROM responds when A19-A12 = 00000000B
A11 to A0 select the internal location within EPROM.
Address range verified: 00000H to 00FFFH

Exam Tip: In GATE problems, always identify how many address pins the memory chip has first. That number of lower address bits goes to the chip directly. The remaining higher bits are decoded to generate chip select. A 4 KB chip uses 12 lower bits; an 8 KB chip uses 13 lower bits.

Quick Revision

• 8086 has 20-bit address bus: addresses 00000H to FFFFFH, total 1 MB addressable space.
• Address decoding separates the 20-bit address into chip select bits (higher) and intra-chip offset bits (lower).
• Full decoding: all address bits used, no aliasing. Partial decoding: fewer bits used, aliasing occurs.
• 74LS138 decoder IC: 3-to-8 line decoder commonly used for chip select generation.
• EPROM sits near FFFFFH (8086 resets to FFFF0H). RAM sits at lower addresses for data and stack.
• BHE and A0 control the high and low byte banks of the 16-bit data bus in 8086 memory interfacing.
• Key formula: Chip pins = log2(size in bytes). Decoding bits = 20 - chip pins.