Control Signals

The 8085 microprocessor generates a set of control signals that coordinate all activity between the CPU and external components such as memory chips, I/O ports, and latches. These signals define what type of bus operation is taking place at any given moment, whether data is being read or written, whether the access is directed at memory or an I/O device, and when the address on the multiplexed bus is valid. Mastering these control signals is essential for hardware system design and for correctly interpreting the timing diagrams that appear in GATE examinations.

Core Concept Explanation

The 8085 generates its control signals from the internal Timing and Control Unit in synchrony with the clock. These signals are not independent; they follow a well-defined sequence determined by the type of machine cycle being executed. The three primary control signals that define all external bus operations are ALE (Address Latch Enable), RD (Read), and WR (Write). Together with the IO/M line, these four signals completely define what the processor is doing on the bus at any instant.

ALE is generated at the start of every machine cycle (T1 state) regardless of the type of cycle. It pulses high for the duration of T1 and returns low at the start of T2. Its sole purpose is to indicate that the multiplexed AD0-AD7 bus currently carries address information and that external hardware should latch this address before the bus switches to data. Without ALE, external circuitry cannot know when to sample the address from the shared bus.

RD is an active-low output signal that goes low during T2 and T3 of a memory read or I/O read cycle. It instructs the addressed device to place its data on the AD0-AD7 lines. The 8085 samples this data at the end of T3. WR is similarly active-low and is asserted during T2 and T3 of a write cycle. It tells the addressed device to accept and store the data that the 8085 has placed on the data bus.

IO/M Signal and Bus Operation Identification

The IO/M signal distinguishes between memory and I/O access. When IO/M is low (logic 0), the current bus cycle is accessing memory. When IO/M is high (logic 1), the current cycle is accessing an I/O port. External address decoding logic uses this signal combined with RD and WR to select either memory chips or I/O port decoders. This separation of memory and I/O space is a key feature of the 8085, giving it separate 64KB memory and 256-port I/O address spaces.

The S0 and S1 status signals provide additional identification of the current bus operation type. These are output pins that reflect the nature of the machine cycle. The combination of IO/M, S1, and S0 uniquely identifies each bus operation: memory read (IO/M=0, S1=1, S0=0), memory write (IO/M=0, S1=1, S0=1), I/O read (IO/M=1, S1=1, S0=0), I/O write (IO/M=1, S1=1, S0=1), and opcode fetch (IO/M=0, S1=0, S0=1). These status lines are useful in systems that need to differentiate opcode fetch from data memory reads, for example in cache controllers or bus monitors.

READY Signal and Wait State Generation

The READY signal is an input to the 8085, driven by external circuitry. During normal fast memory operation, READY is permanently tied high and the 8085 executes every machine cycle without interruption. When slow memory or I/O devices are used, the device asserts READY low to force the 8085 to insert wait states. The 8085 checks the READY line at the falling edge of T2. If READY is low, it inserts a wait state (TW) of one clock period between T2 and T3 and checks again. This repeats until READY goes high, at which point T3 executes and the bus cycle completes normally.

The CLK OUT pin provides the divided-by-2 clock to the rest of the system. All peripheral chips such as the 8155 RAM/IO/Timer and 8255 PPI synchronize their operations to this clock output. The CLK OUT frequency equals the crystal frequency divided by 2. This ensures all components in the 8085 system operate on the same synchronized clock derived from a single crystal source.

Mathematical Expression

The memory access time requirement is determined by the machine cycle timing. In a normal memory read cycle (3 T-states, no wait states), the memory must respond within a specific window. The available memory access time equals the sum of T2 and T3 durations minus the signal propagation delays. Specifically: t_access less than or equal to (2 times T_clock) minus (address setup time plus RD propagation delay plus data setup time). At 3 MHz clock (T = 333 ns), the available access window is approximately 460 ns for most 8085 systems. If memory is slower, wait states must be inserted using the READY line.

Numerical Example

A standard GATE problem gives the 8085 clock frequency and memory access time, and asks how many wait states are required. The calculation involves comparing available access time per T-state with the memory's rated access time.

Given:
Clock frequency: f = 3 MHz → T_clock = 1/3 MHz = 333.3 ns
Memory access time: t_mem = 900 ns
Overhead (address latch + RD propagation + data setup): ~100 ns

Why this formula applies:
In a read cycle, effective time available for memory to respond = T_clock × (T-states in read phase) - overhead
Each wait state adds one T_clock to the read window.

Formula:
Available time per cycle = n × T_clock - overhead
Required: available time ≥ t_mem

Base read phase (T2 + T3) without wait states:
Available = 2 × 333.3 - 100 = 666.6 - 100 = 566.6 ns < 900 ns  [Insufficient]

With 1 wait state (T2 + TW + T3):
Available = 3 × 333.3 - 100 = 999.9 - 100 = 899.9 ns < 900 ns  [Marginally insufficient]

With 2 wait states (T2 + TW + TW + T3):
Available = 4 × 333.3 - 100 = 1333.2 - 100 = 1233.2 ns > 900 ns  [Sufficient]

Calculation:
Minimum wait states needed = 2

Final Answer:
2 wait states must be inserted via READY signal for this memory to work correctly at 3 MHz

Exam Tip: GATE often tests the IO/M, S1, S0 combination table. Memorize: Memory Read = (0,1,0), Memory Write = (0,1,1), I/O Read = (1,1,0), I/O Write = (1,1,1), Opcode Fetch = (0,0,1). Also, ALE is generated in EVERY machine cycle during T1 — it is not exclusive to the opcode fetch cycle. This is a common misconception.

Control Signal Behavior Summary

• ALE is generated in T1 of every machine cycle, not just opcode fetch. It pulses high briefly to indicate valid address on AD0-AD7, then falls low at the start of T2 when the bus transitions to carry data.
• RD goes low (active) during T2 and T3 for any read operation (memory or I/O). WR goes low during T2 and T3 for any write operation. Both are never active simultaneously.
• IO/M remains stable throughout the entire machine cycle. It is set at T1 by the control unit based on the instruction being executed and does not change until the next machine cycle begins.
• The combination of IO/M, RD, and WR uniquely determines the type of bus operation. External interface chips decode these three signals to determine whether to enable memory read, memory write, I/O read, or I/O write circuitry.
• READY must be stable and high before the falling edge of T2 for normal operation. Any system that ties READY permanently high eliminates all wait state capability and may fail with slow memory devices.

Quick Revision

• ALE: active high, generated in T1 of every machine cycle. Used to demultiplex address from AD0-AD7. External latch captures A0-A7 on falling edge of ALE.
• RD (active low): asserted during T2-T3 of any read cycle. Tells memory or I/O to drive data onto the bus.
• WR (active low): asserted during T2-T3 of any write cycle. Tells memory or I/O to accept the data on the bus.
• IO/M: high = I/O access, low = memory access. Stable for the entire machine cycle. Used with RD/WR for full bus operation decode.
• Status lines IO/M, S1, S0 decode table: Memory Read=(0,1,0), Memory Write=(0,1,1), I/O Read=(1,1,0), I/O Write=(1,1,1), Opcode Fetch=(0,0,1).
• READY: input to 8085 sampled at falling edge of T2. If low, TW wait states are inserted. Each TW = 1 T-state = 1/f seconds.
• Wait states needed = ceiling of [(t_mem - available_time) / T_clock]. Always add overhead (signal propagation delays, ~100 ns) when computing available memory access time.