Demultiplexing Bus

The 8085 microprocessor uses a multiplexed address/data bus on its lower 8 lines (AD0–AD7), meaning these pins carry both address information and data during different phases of a machine cycle. To use both signals independently, the address must be latched out before the data appears. Understanding how demultiplexing works is essential for hardware interfacing and is a frequently tested topic in GATE and university exams.

Why the 8085 Uses a Multiplexed Bus

The 8085 is an 8-bit microprocessor with a 16-bit address space (64 KB). To address this range, it needs 16 address lines. However, to reduce pin count and chip area, Intel designed the lower byte of the address bus (A0–A7) to share the same physical pins as the data bus (D0–D7). These shared pins are called AD0–AD7 (Address/Data multiplexed lines). The upper 8 address lines A8–A15 are always dedicated to the address bus and are never shared.

During the first clock cycle (T1) of any machine cycle, the 8085 places the lower 8 bits of the address on AD0–AD7. After this, the same pins switch to carry data. Since both signals cannot coexist on the same wire simultaneously, a mechanism is needed to capture the address before it disappears. This mechanism is called bus demultiplexing.

Role of the ALE Signal

The 8085 provides a dedicated control signal called ALE (Address Latch Enable) on pin 30. This signal goes HIGH during the T1 state of every machine cycle, exactly when valid address information is present on AD0–AD7. External hardware uses this pulse to latch (capture and hold) the address before AD0–AD7 switches to data mode.

The ALE pulse is brief and occurs only at the beginning of each machine cycle. The external latch must capture the address during this HIGH pulse and continue to present it stably on its output pins for the remainder of the cycle. This way, memory or I/O devices always receive a stable 16-bit address.

74LS373 Latch: The Standard Demultiplexer

The most commonly used external latch for 8085 demultiplexing is the 74LS373 octal transparent latch. It has 8 D-type latches with a common enable input (G). When G is HIGH, the outputs follow the inputs (transparent mode). When G goes LOW, the last input state is captured and held regardless of any further input changes.

In the 8085 system, the AD0–AD7 lines connect to the D inputs of 74LS373, and the ALE signal connects to the G (enable) pin. When ALE is HIGH, the address passes through transparently. The moment ALE falls LOW, the latch freezes the address on its Q outputs (A0–A7). These Q outputs then serve as the stable lower address byte for the rest of the machine cycle.

Complete Bus Architecture After Demultiplexing

After demultiplexing, the system has a full 16-bit address bus: A8–A15 directly from the 8085, and A0–A7 from the 74LS373 Q outputs. The AD0–AD7 pins of the 8085 then operate as the 8-bit data bus during T2 and T3 states. Memory chips receive the complete address on A0–A15 and exchange data through D0–D7.

Mathematical Timing Context

In a typical 8085 system running at 3 MHz, each clock period T is approximately 333 ns. The T1 state lasts one clock period. The ALE pulse is valid for most of T1, giving the latch approximately 250–300 ns to capture the address. The 74LS373 has a typical propagation delay of 18 ns, which is well within this window. The hold time of the latch (time the address must remain stable after ALE goes LOW) is around 5 ns, and the 8085 guarantees a hold time of at least 10 ns, ensuring reliable address capture.

Given:
  Clock frequency of 8085 = 3 MHz
  One clock period T = 1 / 3 MHz = 333 ns
  ALE is HIGH for approximately 80% of T1
  74LS373 propagation delay = 18 ns
  74LS373 setup time = 5 ns

Why this formula applies:
  The latch must capture address before ALE falls. Available capture window = ALE pulse width.

Formula:
  ALE pulse width ≈ 0.8 × T

Substitution:
  ALE pulse width ≈ 0.8 × 333 ns

Calculation:
  ALE pulse width ≈ 266 ns
  Time available for latch = 266 ns − 18 ns (prop delay) − 5 ns (setup) = 243 ns margin

Final Answer:
  Latch has ~243 ns margin, comfortably exceeding the 74LS373 timing requirements at 3 MHz.

Exam Tip: In GATE questions, ALE going HIGH always marks the beginning of a machine cycle and the presence of a valid address on AD0–AD7. Never confuse ALE with the WR or RD strobe signals. The latch output (Q) gives A0–A7, not the AD0–AD7 pins directly.

• AD0–AD7 carry the lower address byte (A0–A7) during T1 state when ALE is HIGH.
• ALE falling LOW triggers the 74LS373 latch to freeze A0–A7 on its outputs.
• After T1, AD0–AD7 becomes the 8-bit bidirectional data bus (D0–D7).
• A8–A15 are always address lines and do not require latching.
• The complete 16-bit address bus = A8–A15 (direct) + Q0–Q7 of 74LS373 (latched A0–A7).

Quick Revision

• AD0–AD7 are multiplexed: carry address during T1, data during T2/T3.
• ALE (pin 30) goes HIGH during T1 to indicate valid address on AD0–AD7.
• 74LS373 octal latch is used to demultiplex: ALE connects to G (enable) pin.
• When ALE goes LOW, the latch captures and holds A0–A7 for the rest of the machine cycle.
• A8–A15 are always dedicated address lines; only lower byte is multiplexed.
• Key formula: ALE pulse width ≈ 0.8 × T, where T = 1/f_clock.
• Exam trap: ALE is not an interrupt or control signal for memory read/write; it is strictly for address latching timing.