SPI

SPI (Serial Peripheral Interface) is a synchronous serial communication protocol designed for short-distance high-speed communication between a master device and one or more peripheral slave devices. Unlike UART which is asynchronous, SPI uses a dedicated clock line generated by the master to synchronize data transfer. This eliminates baud rate mismatch issues entirely and allows much higher data rates, often reaching tens of megabits per second. SPI is used for SD cards, flash memory, ADCs, DACs, display controllers, and many sensor modules in embedded systems.

Core Concept of SPI

SPI uses four signal lines. MOSI (Master Out Slave In) carries data from the master to the slave. MISO (Master In Slave Out) carries data from the slave back to the master. SCLK is the clock generated by the master that synchronizes data sampling on both sides. CS (Chip Select), also called NSS or SS, is driven LOW by the master to activate a specific slave. Multiple slaves share MOSI, MISO, and SCLK lines but each has its own CS line, so only one slave is active at a time.

SPI is a full-duplex protocol: data can flow in both directions simultaneously during the same clock cycle. The master and slave each have an 8-bit (or 16-bit) shift register. On each clock edge, one bit is shifted out from the master to the slave on MOSI while simultaneously one bit is shifted in from the slave to the master on MISO. After 8 clock cycles, a full byte has been exchanged in both directions. Even if the slave has no meaningful data to send back, it still shifts out bits (usually zeroes or a status register) during every transaction.

The behavior of SPI at clock edges is defined by two parameters: CPOL (Clock Polarity) and CPHA (Clock Phase). CPOL defines the idle state of the clock line: CPOL=0 means clock is LOW when idle, CPOL=1 means clock is HIGH when idle. CPHA defines which edge is used for data capture: CPHA=0 means data is sampled on the first edge, CPHA=1 means data is sampled on the second edge. The four combinations of CPOL and CPHA define four SPI modes (Mode 0 through Mode 3). The master and slave must use the same mode, as specified in the slave device datasheet.

Mathematical Expression

The SPI clock frequency is directly set by the master, typically as a power-of-two division of the master peripheral clock. There is no baud rate formula involving oscillator error as in UART, because the slave samples data on the exact edges of the master-generated clock. The maximum SPI clock frequency is limited by the slave device specification and the PCB trace length and capacitance. The time to transfer one byte of data at a given SCLK frequency is calculated directly as 8 clock periods, and a full transaction including CS assertion and deassert times is slightly longer.

Transfer time for N bits: T_transfer = N / f_SCLK. Effective data throughput in bits per second equals f_SCLK for continuous streaming (no CS overhead between bytes). When individual transactions are short and CS must be cycled between each byte, the overhead of CS setup and hold times (typically a few SCLK cycles as specified by the slave datasheet) reduces actual throughput below f_SCLK.

Practical Understanding

SPI is significantly faster than UART or I2C for the same peripheral clock, because there are no address bits, no acknowledgment bits, and no start-stop overhead within a transaction. The tradeoff is that SPI requires more wires, especially when multiple slaves are present, since each additional slave needs its own CS line. In contrast, I2C uses only two wires and supports up to 127 devices through addressing, which is a hardware advantage for designs with many low-speed peripherals.

One practical complication is the SPI mode mismatch problem. If the master is configured in Mode 0 (CPOL=0, CPHA=0) but the slave expects Mode 3 (CPOL=1, CPHA=1), data will be corrupted silently without any error reporting. SPI has no error detection, no acknowledgment, and no flow control. It is the programmer's responsibility to ensure that CPOL, CPHA, bit order (MSB or LSB first), and SCLK frequency are all configured correctly according to the slave's datasheet before communication begins.

Given:
Master peripheral clock f_PCLK = 48 MHz
SPI prescaler = 8
Data to transfer = 3 bytes
SPI Mode = 0 (CPOL = 0, CPHA = 0)

Why this formula applies:
SPI clock is derived directly from peripheral clock via prescaler.
Transfer time = number of bits / SCLK frequency.

Formula:
f_SCLK = f_PCLK / SPI_prescaler
T_per_bit = 1 / f_SCLK
T_transfer = (N_bits) / f_SCLK

Substitution:
f_SCLK = 48,000,000 / 8 = 6 MHz
T_per_bit = 1 / 6,000,000
N_bits = 3 bytes x 8 bits = 24 bits
T_transfer = 24 / 6,000,000

Calculation:
f_SCLK = 6 MHz
T_per_bit = 0.167 microseconds
T_transfer = 24 / 6,000,000 = 4 microseconds

Final Answer:
SPI clock = 6 MHz
Time to transfer 3 bytes = 4 microseconds (excluding CS overhead)

Exam Tip: SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1) sample data on the same relative edge (leading for Mode 0, trailing for Mode 3) but with different idle clock levels. A common MCQ gives CPOL and CPHA values and asks which edge captures data.

• SPI uses 4 lines: MOSI (master to slave), MISO (slave to master), SCLK (master clock), CS (active LOW select).
• Full-duplex: 1 bit shifts out on MOSI while 1 bit shifts in on MISO on every clock edge simultaneously.
• CPOL sets clock idle level (0=LOW, 1=HIGH). CPHA sets capture edge (0=first edge, 1=second edge).
• Four modes (0-3) from CPOL/CPHA combinations. Master and slave must match.
• Transfer time = N_bits / f_SCLK. No addressing, no ACK, no flow control — faster but less error-safe than I2C.
• Each additional slave needs its own CS line; no address-based selection.

Quick Revision

• SPI is synchronous: master generates SCLK, so no baud rate mismatch is possible.
• 4 wires: MOSI, MISO, SCLK, CS. Full duplex on every clock cycle.
• f_SCLK = f_PCLK / prescaler. Transfer time for N bits = N / f_SCLK.
• CPOL=0: idle LOW. CPOL=1: idle HIGH. CPHA=0: sample on first edge. CPHA=1: sample on second edge.
• Mode 0 (most common): CPOL=0, CPHA=0 — sample on rising edge, idle LOW.
• No error detection, no ACK, no flow control — faster than I2C/UART but all configuration must be correct.
• Exam trap: Mode 0 and Mode 3 both sample on the same relative edge type but differ in idle clock level. Do not confuse them.