DAC Interfacing

R-2R ladder, PWM filtering.

Darshan N
Updated: 19 March 2026
8 min read

A Digital-to-Analog Converter (DAC) is an essential peripheral in embedded systems whenever a microcontroller needs to produce a continuously varying voltage output. Applications range from audio signal generation and motor speed control to waveform synthesis and display driving. Understanding how to interface a DAC correctly is a core competency for embedded systems engineers.

DAC Interfacing OverviewMicro-controllerDAC IC /R-2R LadderOp-Amp /BufferAnalogLoadDigitalBitsAnalog VMethod 1: R-2R LadderResistors only, n-bit outputMethod 2: PWM FilterRC low-pass smoothingMethod 3: Dedicated DACIC e.g. DAC0808, MCP4921SPI / I2CSerial interface DACsOutput Voltage FormulaVout = (D / 2^n) x VrefD = digital input, n = number of bits, Vref = reference voltage
Figure 1: DAC interfacing methods and signal flow from microcontroller to analog output

Core Concept Explanation

A microcontroller operates entirely in the digital domain, processing binary values. However, the physical world is analog. Actuators, speakers, motors, and display backlights all require a continuously variable voltage rather than a simple high-low signal. A DAC bridges this gap by converting an n-bit digital code into a proportional analog voltage.

The two most common interfacing approaches in embedded systems are the R-2R resistor ladder network and PWM-based DAC using a low-pass filter. The R-2R ladder uses only two resistor values (R and 2R) in a repeating network connected directly to GPIO pins. Each bit contributes a weighted current to the summing node, and the output voltage steps change in equal increments called the least significant bit (LSB) voltage.

In a PWM-based approach, the microcontroller generates a pulse-width modulated signal at a fixed frequency. An RC low-pass filter then averages this signal, producing a DC level proportional to the duty cycle. If the duty cycle is 50%, the output settles near Vcc/2. This method requires no external DAC IC but the output ripple must be controlled by choosing the RC time constant carefully relative to the PWM frequency.

Dedicated DAC ICs such as the DAC0808 (parallel interface), MCP4921 (SPI), or MCP4725 (I2C) provide better resolution, lower noise, and internal voltage references. These are preferred in precision applications. The microcontroller sends a digital word via the communication bus, and the DAC internally performs the conversion.

Mathematical Expression

For any n-bit DAC, the analog output voltage is determined by the digital input code D, the number of bits n, and the reference voltage Vref. The general expression is given below. This formula applies to both R-2R ladders and dedicated DAC ICs operating in unipolar mode.

The resolution of a DAC is defined as the smallest change in output voltage per LSB step: Resolution = Vref / 2^n. For a 3.3V reference and 8-bit DAC, one LSB corresponds to 3.3/256 = 12.89 mV. Higher bit count gives finer resolution but also demands more GPIO lines in the case of R-2R, or higher clock precision in the case of serial DACs.

The full-scale output is never exactly Vref. For an n-bit DAC with all bits set (D = 2^n - 1), Vout = Vref x (1 - 1/2^n). This means the output approaches but never reaches Vref, an important distinction in calibration and scaling calculations.

Practical Understanding

In R-2R ladder implementation, the GPIO pins of the microcontroller drive the ladder directly. The output impedance of GPIO pins must be low compared to the resistor values, otherwise bit weighting errors occur. Typical R values range from 10k to 22k ohms. The output of the ladder is high impedance and must be buffered with an op-amp voltage follower before driving any load.

For PWM-based DAC, the choice of RC values is critical. The RC time constant should be at least 10 times larger than the PWM period to reduce ripple below 1%. For a PWM frequency of 10 kHz (period = 0.1 ms), the RC time constant should be at least 1 ms. Using R = 10k and C = 100nF gives tau = 1 ms, which is a practical starting point.

When using dedicated SPI DACs like the MCP4921, the microcontroller sends a 16-bit command word containing configuration bits and the 12-bit data value. The DAC latches the output on the chip select rising edge. Ensuring correct SPI mode (CPOL, CPHA) and clock speed within the DAC's maximum specification is essential for correct operation.

Example
Given:
DAC resolution n = 8 bits
Vref = 5V
Digital input D = 178

Why this formula applies:
Unipolar DAC output is directly proportional to input code fraction.

Formula:
Vout = (D / 2^n) x Vref

Substitution:
Vout = (178 / 256) x 5

Calculation:
Vout = 0.6953 x 5 = 3.477 V
Resolution per LSB = 5 / 256 = 19.53 mV

Final Answer:
Vout = 3.477 V, LSB step = 19.53 mV
Exam Tip: In GATE and university exams, DAC resolution questions often ask for LSB voltage, not full-scale voltage. Remember: Resolution = Vref / 2^n. Full-scale = Vref x (1 - 1/2^n). Never write full-scale as Vref directly.
R-2R Ladder Network (3-bit) and PWM FilterR-2R Ladder (3-bit)Bit2 (MSB)2R2R2RVoutBit1RBit0 (LSB)R2RGNDAll 2R bottom nodes to GNDGNDPWM Low-Pass FilterPWM OutRCGNDVout (DC)Vout_avg = Duty Cycle x Vcctau = RC much greater than PWM periodComparison: R-2R vs PWM vs Dedicated DAC ICFeatureR-2R LadderPWM FilterDAC ICResolutionn bits (GPIO count)8-16 bits (PWM res)8-16 bitsSpeedFastLimited by RCFast (SPI/I2C)NoiseLowRipple presentVery lowCostVery lowVery lowLow to moderate
Figure 2: R-2R ladder network mechanism, PWM RC filtering, and method comparison for DAC interfacing

Mechanism and Working Steps

  • In R-2R ladder, each GPIO pin drives a 2R resistor. The binary-weighted current summing at the output node produces a voltage proportional to the digital code. MSB contributes half of full scale, next bit contributes quarter, and so on.
  • In PWM-based DAC, the timer peripheral of the microcontroller sets the duty cycle register. The RC filter integrates the square wave into a smooth DC level. Output ripple decreases as the ratio of RC time constant to PWM period increases.
  • For serial DAC ICs, the microcontroller initializes the SPI or I2C peripheral, sends the device address (I2C) or asserts chip select (SPI), and transmits the digital word. The DAC converts it internally and holds the output until a new word arrives.
  • The output buffer op-amp in R-2R implementation must have rail-to-rail output capability if the full voltage range is needed. Unity gain configuration prevents load current from disturbing the ladder voltages.
  • Step size (LSB voltage) directly determines the minimum controllable change in output. Choosing DAC resolution should match the system requirement: 8-bit is sufficient for audio volume, 12-bit or higher is needed for precision analog control.

Quick Revision

  • DAC converts n-bit digital code to proportional analog voltage: Vout = (D / 2^n) x Vref.
  • Resolution = Vref / 2^n. An 8-bit DAC at 5V gives 19.53 mV per LSB.
  • Full-scale output = Vref x (2^n - 1) / 2^n, never equals Vref exactly.
  • R-2R ladder uses only R and 2R resistors, requires n GPIO lines, fast but needs output buffer.
  • PWM DAC needs RC low-pass filter. Output ripple reduces when RC time constant is much larger than PWM period.
  • Dedicated DAC ICs (MCP4921-SPI, MCP4725-I2C) give precision, low noise, and internal reference options.
  • Exam trap: Do not equate full-scale voltage to Vref. The maximum output is always one LSB less than Vref.

DAC Interfacing Quiz

Test your knowledge of R-2R ladder networks and PWM-based DAC techniques.

Question 1 of 3

Q1.In an R-2R ladder DAC, what is the Thevenin equivalent resistance seen at the output node regardless of the number of bits?