PWM Generation

Pulse Width Modulation (PWM) is a technique used in embedded systems to control the effective power delivered to a load by switching a digital output on and off at a fixed frequency while varying the fraction of time the signal stays high. Instead of converting a digital signal to a true analog voltage using a DAC, PWM approximates analog control through time-averaging, making it computationally cheap and hardware-efficient. It is used extensively in motor speed control, LED brightness adjustment, servo positioning, and DC-DC converters.

Core Concept of PWM Generation

A timer peripheral inside a microcontroller generates PWM by comparing a continuously running counter value against a user-set threshold called the compare register. The timer is loaded with a value that determines the PWM period, and the compare register value determines when within that period the output transitions from high to low. The ratio of the compare value to the period value is the duty cycle, expressed as a percentage.

Most microcontrollers implement PWM using one of two timer modes. In edge-aligned PWM, the counter counts from 0 up to the auto-reload register (ARR) value and resets. The output pin is set high at the start of each period and cleared when the counter reaches the compare value (CCR). In center-aligned PWM, the counter counts up and then down, producing a symmetric waveform that reduces harmonic distortion, which is beneficial in motor control applications.

The PWM frequency is determined by the timer clock frequency divided by the prescaler and the ARR value. Choosing the correct frequency matters because too low a frequency causes visible LED flicker or audible motor noise, while too high a frequency increases switching losses and may exceed the timer hardware limit.

Mathematical Expression

Given a timer clock frequency of f_clk, a prescaler value PSC, and an auto-reload register value ARR, the PWM output frequency is calculated using a direct formula. The compare register CCR then sets the pulse width. Understanding this relationship allows precise control of both frequency and duty cycle independently, which is essential for applications like servo control where a specific frequency and a specific pulse width must both be maintained simultaneously.

The PWM frequency is given by: f_PWM = f_clk / ((PSC + 1) x (ARR + 1)). The duty cycle in percent is: D = (CCR / (ARR + 1)) x 100. The average output voltage across a resistive load is: V_avg = D x V_supply. These three expressions are the foundation of all PWM configuration tasks in embedded systems and GATE questions.

Practical Understanding

In a typical ARM Cortex-M microcontroller such as STM32, the timer peripheral has dedicated output compare channels. Each channel has its own CCR register but shares the ARR with other channels on the same timer. This means multiple PWM outputs from the same timer always share the same frequency but can have independent duty cycles, a useful property for RGB LED control or three-phase motor driving.

For motor control, increasing PWM duty cycle increases the average current through the motor winding, raising speed. For LED dimming, the human eye integrates brightness over time so a 30% duty cycle PWM signal appears about 30% as bright as full illumination, as long as the PWM frequency exceeds approximately 50 Hz to prevent visible flicker. Modern LED drivers typically use frequencies above 1 kHz.

Dead time insertion is an important practical concern in H-bridge motor drivers. When switching between the high-side and low-side transistors, a brief period called dead time must be enforced during which both switches are off to prevent a short circuit condition called shoot-through. Advanced timer peripherals include hardware dead-time generation for this purpose.

Given:
Timer clock f_clk = 72 MHz
Prescaler PSC = 71
Auto-reload register ARR = 999
Compare register CCR = 300
Supply voltage V_supply = 3.3 V

Why this formula applies:
PWM frequency depends on timer clock divided by prescaler and period count.
Duty cycle is the fraction of the period for which output is HIGH.

Formula:
f_PWM = f_clk / ((PSC + 1) x (ARR + 1))
Duty Cycle D = (CCR / (ARR + 1)) x 100
V_avg = D x V_supply

Substitution:
f_PWM = 72,000,000 / ((71 + 1) x (999 + 1))
D = (300 / 1000) x 100
V_avg = 0.30 x 3.3

Calculation:
f_PWM = 72,000,000 / (72 x 1000) = 72,000,000 / 72,000 = 1000 Hz = 1 kHz
D = 30%
V_avg = 0.99 V

Final Answer:
PWM Frequency = 1 kHz
Duty Cycle = 30%
Average Output Voltage = 0.99 V

Exam Tip: In GATE and university exams, when PSC and ARR are given, always add 1 to each before multiplying. Forgetting the +1 correction is the most common error and changes frequency by a significant margin.

• The timer counter increments on every prescaled clock tick from 0 to ARR, then resets.
• The output pin is driven HIGH when CNT is less than CCR and LOW when CNT is equal to or greater than CCR.
• Changing ARR adjusts PWM frequency; changing CCR adjusts duty cycle without affecting frequency.
• Center-aligned mode makes the counter count up then down, producing a symmetric waveform useful for motor control.
• Multiple channels on one timer share the same ARR but have independent CCR values, giving independent duty cycles at a common frequency.

Quick Revision

• PWM controls average power by varying the fraction of time the signal stays HIGH at a fixed frequency.
• f_PWM = f_clk / ((PSC + 1) x (ARR + 1)) — always include the +1 correction.
• Duty Cycle D = (CCR / (ARR + 1)) x 100 percent.
• Average voltage = D x V_supply for resistive loads.
• Edge-aligned mode: counter counts 0 to ARR. Center-aligned mode: counter counts up then down.
• Dead time is inserted between high-side and low-side switching to prevent shoot-through in H-bridge circuits.
• Exam trap: forgetting +1 in both PSC and ARR when calculating frequency is the most common mistake.