Input Capture

Measuring the frequency or pulse width of an external signal is a common requirement in embedded systems, whether for reading a tachometer, decoding a PWM signal from a sensor, or measuring sonar echo time. Input capture is a hardware feature of STM32 timers that automatically records the counter value at the exact moment a GPIO transition occurs, enabling precise timing measurements without software latency.

Core Concept: How Input Capture Works

In input capture mode, a timer channel is configured as an input rather than an output. When the selected edge (rising, falling, or both) is detected on the GPIO pin connected to the timer channel, the current value of the CNT register is automatically copied into the CCRx register (Capture/Compare Register x). The CPU can then read this captured timestamp to calculate timing information.

The key advantage is that the capture happens in hardware at the exact clock edge. There is no software delay involved in reading the transition time. This allows measurement accuracy down to a single timer clock cycle. The CCxIF flag (Capture/Compare Interrupt Flag) is set when a capture occurs, and an interrupt can be generated to read the CCRx value before the next capture overwrites it.

The input channel routing is configured through the CCMR register (Capture/Compare Mode Register). The CCxS bits select whether the channel is in input or output mode and which input source it reads. Prescaler bits (ICxPSC) allow capturing only every 2nd, 4th, or 8th edge, which is useful for very high frequency signals.

Mathematical Expression

Pulse width measurement uses two captures on the same channel configured for both edges, or two channels. If the first rising edge captures CCR value t1 and the falling edge captures t2:

Pulse width (seconds) = (t2 - t1) / Timer_Clock_Hz. If t2 < t1, a counter overflow occurred and the difference must account for the ARR+1 rollover: Corrected_diff = (ARR + 1 - t1) + t2. Signal period is measured as the difference between two consecutive rising edges: Period = (t3 - t1) / Timer_Clock_Hz. Frequency = 1 / Period.

Practical Understanding

A common application is measuring the frequency of an encoder or tachometer. The timer runs continuously at a known frequency, and each pulse of the encoder signal causes a capture. The difference between consecutive captures directly gives the pulse period.

Overflow handling is important for low-frequency signals. If the signal period is longer than the timer's maximum count period, CNT overflows before the next edge arrives. The update interrupt should be used to count overflows, and the total elapsed time calculated as: Total_time = (overflow_count x (ARR+1) + t2 - t1) / Timer_Clock.

Given:
Timer clock = 1 MHz (after prescaler)
First rising edge capture: t1 = 12,400
Falling edge capture: t2 = 17,900
Next rising edge: t3 = 32,400
No overflow between captures

Why this formula applies:
Pulse width = time between rising and falling edge captures.

Formula:
Pulse_width = (t2 - t1) / Timer_Clock
Period = (t3 - t1) / Timer_Clock
Frequency = 1 / Period

Substitution:
Pulse_width = (17900 - 12400) / 1,000,000 = 5500 / 1,000,000
Period = (32400 - 12400) / 1,000,000 = 20000 / 1,000,000

Calculation:
Pulse_width = 5.5 ms
Period = 20 ms
Frequency = 1 / 0.020

Final Answer:
Pulse width = 5.5 ms, Signal frequency = 50 Hz

Exam Tip: When an overflow occurs between two captures, the actual difference is: diff = (ARR + 1) - t1 + t2. Forgetting to handle overflow is the most common input capture coding mistake and a frequent exam question. Always check the overflow (UIF) flag alongside the capture flag.

Input Capture Register Configuration

• CCxS bits in CCMR must be set to 01 to configure the channel as input; default is output mode.
• ICxPSC prescaler captures every 1st, 2nd, 4th, or 8th edge, reducing interrupt frequency for fast signals.
• ICxF filter bits reject glitches shorter than N clock cycles, controlled by the filter coefficient.
• Overcapture occurs when a second edge arrives before CCRx is read; CC1OF flag is set as a warning.
• PWM input mode uses two channels on the same pin to simultaneously capture both pulse width and period.

Quick Revision

• Input capture stores CNT value into CCRx register automatically on each GPIO edge event.
• Pulse width = (t_fall - t_rise) / Timer_Clock. Period = (t_rise2 - t_rise1) / Timer_Clock.
• Overflow correction: diff = (ARR+1 - t1) + t2 when counter wraps between captures.
• CCxS=01 in CCMR selects input mode. CC1P in CCER sets edge polarity.
• ICxPSC prescaler useful for high-frequency inputs to reduce interrupt load.
• Overcapture flag (CC1OF) warns that a new capture occurred before previous CCRx was read.
• PWM input mode: two channels on one pin capture both rising and falling edges simultaneously.