PCB Design Basics

A printed circuit board (PCB) is the physical platform that connects electronic components using conductive traces, allowing an embedded system to function as a complete unit. Designing a PCB correctly is as critical as writing correct firmware. Errors in PCB layout cause signal integrity failures, electromagnetic interference, power delivery problems, and unreliable operation. PCB design fundamentals are important for embedded hardware engineers and are tested in electronics and instrumentation engineering examinations.

Core Concept: From Schematic to Layout

PCB design begins with a schematic that represents the logical connectivity between components. The schematic does not specify physical positions or trace paths. It captures which pin of each component connects to which pin of every other component, defined through named nets.

The schematic is then exported as a netlist, a file that maps every component and its pins to the nets they belong to. The PCB layout tool imports this netlist and displays components as footprints with ratsnest lines (thin lines showing required but unrouted connections). The designer then places components and routes traces to convert ratsnest lines into physical copper connections.

PCB Layers

A PCB is built from multiple layers of copper foil and insulating substrate (typically FR4 fiberglass). A simple two-layer board has a top copper layer and a bottom copper layer. High-speed and complex embedded designs use four or more layers. In a four-layer board, the inner two layers are typically dedicated to a solid ground plane and a power plane. Signal traces route on the outer two layers.

A dedicated ground plane provides a low-impedance return path for all signal currents, which is critical for signal integrity and EMI reduction. The proximity of signal traces to the ground plane also creates a controlled impedance environment, which is important for high-frequency and high-speed digital signals.

Mathematical Expression: Trace Impedance

For controlled impedance routing, the characteristic impedance of a microstrip trace (a trace on the outer layer above a ground plane) can be approximated using the IPC-2141 formula. The impedance depends on trace width, trace thickness, dielectric thickness, and the relative permittivity of the substrate material. Most high-speed digital standards (HDMI, USB, Ethernet) target 50 ohms or 90 ohms differential impedance.

The approximate formula for a microstrip trace is: Z0 = (87 / sqrt(Er + 1.41)) x ln(5.98 x H / (0.8 x W + T)), where Z0 is characteristic impedance in ohms, Er is the relative permittivity of the substrate, H is the dielectric thickness, W is the trace width, and T is the trace thickness. All dimensions are in the same units.

Component Placement Rules

Good component placement is the foundation of a good PCB. Decoupling capacitors must be placed as close as possible to the power pins of every IC. They suppress high-frequency noise on the power supply by providing a local charge reservoir. A decoupling capacitor placed even a few centimeters away loses its effectiveness due to parasitic trace inductance.

Crystal oscillators and other sensitive analog components must be kept away from high-speed digital traces to avoid coupling interference. Power components such as voltage regulators and switching converters must be placed near the board edge with short, wide traces to carry high currents without excessive resistive voltage drop.

EMI Rules and Ground Planes

Electromagnetic interference (EMI) in PCBs originates primarily from current loops. Every signal trace has a return current path, and that return current follows the path of least impedance, which at high frequencies is the path directly below the trace on the nearest ground plane. A split or cut in the ground plane forces the return current to take a longer path, forming a larger loop antenna that radiates EMI.

The golden rule is to never route high-speed signal traces across splits in the ground plane. Via stitching is used to maintain ground plane continuity across board sections. The area of a current loop is directly proportional to EMI radiation, so minimizing loop areas through good layer stack design and solid ground planes is the primary EMI mitigation strategy.

Numerical Example

Trace resistance determines the voltage drop along a power distribution trace. For current-carrying traces on a PCB, the resistance is calculated from the resistivity of copper, the trace cross-sectional area, and the trace length. This determines whether a wider trace is needed for the current requirement.

Given:
  Trace length (L) = 50 mm = 0.05 m
  Trace width (W) = 1 mm = 0.001 m
  Trace thickness (T) = 35 um = 0.000035 m (1 oz copper)
  Resistivity of copper (rho) = 1.72e-8 ohm-m
  Current (I) = 1 A

Why this formula applies:
  Trace resistance causes voltage drop (IR drop) on power traces.
  Excessive drop leads to brownout in powered ICs.

Formula:
  R = rho x L / A,  where A = W x T (cross-sectional area)

Substitution:
  A = 0.001 x 0.000035 = 3.5e-8 m^2
  R = (1.72e-8 x 0.05) / 3.5e-8

Calculation:
  R = (8.6e-10) / (3.5e-8)
  R ≈ 0.0246 ohms
  Voltage drop = I x R = 1 x 0.0246 ≈ 24.6 mV

Final Answer:
  Trace resistance ≈ 24.6 mohm, causing 24.6 mV drop at 1 A.
  Acceptable for most 3.3V rails (< 1% drop). Adequate trace width.

Exam Tip: In PCB questions, remember that 1 oz copper corresponds to approximately 35 micrometer trace thickness, and the trace resistance formula R = rho x L / (W x T) is directly applicable. A wider trace reduces both resistance and inductance. For EMI, the critical concept is that return current follows the ground plane directly below the signal trace, and any discontinuity in the plane forces the return current to deviate, increasing loop area and EMI.

Mechanism Explained

• Return current flows through the ground plane directly below the signal trace. Any split or cut in the ground plane forces return current to reroute, forming a larger loop that radiates EMI.
• Decoupling capacitors must be placed within 1 to 2 mm of the IC's power supply pin. Longer traces introduce parasitic inductance that degrades filtering effectiveness.
• Trace resistance: R = rho x L / (W x T). Wider traces reduce both resistance and inductance, enabling higher current flow with lower voltage drop and better signal integrity.
• Characteristic impedance of a microstrip trace depends on trace width, dielectric height, and substrate permittivity. Most high-speed standards target 50 ohm single-ended or 90 ohm differential.
• Design Rule Check (DRC) must be run before generating Gerber files. DRC validates minimum clearances, trace widths, via sizes, and annular ring dimensions according to the board manufacturer's capabilities.

Quick Revision

• PCB design flow: Schematic → Netlist → Component Placement → Routing → DRC → Gerber output.
• 4-layer stack: Layer 1 (signal), Layer 2 (ground plane), Layer 3 (power plane), Layer 4 (signal). Inner planes provide return paths and shielding.
• Trace resistance: R = rho x L / (W x T). For 1 oz copper (35 um thick), rule of thumb is 1 A per mm of trace width.
• Decoupling capacitors: 100 nF ceramic, placed within 1-2 mm of every IC power pin to suppress power supply noise.
• Never route high-speed signals across ground plane splits. This forces return current to detour, creating large EMI-radiating loops.
• Characteristic impedance Z0 of a microstrip depends on trace width W, dielectric height H, thickness T, and permittivity Er of the substrate.
• GATE trap: Increasing trace width reduces both resistance and characteristic impedance simultaneously. For controlled impedance, width must be calculated precisely.