Memory Map

The memory map of ARM Cortex-M defines how the processor's 4 GB addressable space is divided into fixed regions for code, data, peripherals, and system configuration. This map is standardized across all Cortex-M devices, which is why firmware ported between different vendors (STMicroelectronics, NXP, TI) can use the same base addresses for the NVIC, SysTick, and system control block.

Core Concept Explanation

The Cortex-M memory map divides the 32-bit address space of 4 GB into eight equal 512 MB regions, each with a defined purpose. This layout is defined in the ARMv7-M architecture reference manual and is fixed for all Cortex-M3/M4 implementations. Chip vendors can only place their specific Flash, SRAM, and peripheral registers within the designated regions; they cannot change which region a particular address class occupies.

The Code region (0x00000000 to 0x1FFFFFFF) is where executable instructions are fetched from via the I-Code and D-Code buses. Flash memory on most Cortex-M MCUs starts at 0x08000000 (STM32) or 0x00000000 (LPC series), both within this region. The vector table, which contains the initial MSP value and exception handler addresses, is located at the start of the Code region by default, though it can be relocated using the VTOR (Vector Table Offset Register).

The SRAM region (0x20000000 to 0x3FFFFFFF) holds writable data: stack, heap, global variables, and DMA buffers. While code can also be executed from SRAM (by copying it there from Flash), SRAM access goes through the System bus rather than the I-Code bus, making it slightly less efficient for code execution than Flash with cache.

Peripheral and PPB Regions

The Peripheral region (0x40000000 to 0x5FFFFFFF) contains memory-mapped registers for all on-chip peripherals: UART, SPI, I2C, GPIO, ADC, timers, and DMA controllers. Firmware accesses peripherals by reading and writing to specific addresses within this region. The AHB and APB bridge addresses determine which peripheral bus a given address falls on.

The Private Peripheral Bus (PPB) region (0xE0000000 to 0xFFFFFFFF) is the most critical region for firmware engineers. It contains the core system registers: SysTick timer at 0xE000E010, NVIC interrupt control registers at 0xE000E100, System Control Block (SCB) at 0xE000ED00, and MPU at 0xE000ED90. These addresses are identical on every Cortex-M device from any vendor, making CMSIS header files vendor-independent for these core peripherals.

Bit-Band Regions

The bit-banding feature provides atomic bit manipulation without read-modify-write sequences. The first 1 MB of the SRAM region (0x20000000 to 0x200FFFFF) and the first 1 MB of the Peripheral region (0x40000000 to 0x400FFFFF) are defined as bit-band regions. Each bit in these 1 MB areas maps to one full 32-bit word in the corresponding 32 MB alias region.

Writing the value 1 to a bit-band alias word atomically sets the corresponding bit in the target byte. Writing 0 clears it. This is done in a single bus transaction and is inherently interrupt-safe, which is valuable for setting or clearing peripheral control bits without disabling interrupts. The alias address calculation for a given bit is: Alias address = Alias base + (byte offset x 32) + (bit number x 4).

Mathematical Expression

The bit-band alias address formula maps a specific bit to its alias word address. For the SRAM bit-band region: Alias address = 0x22000000 + (byte_offset x 32) + (bit_number x 4). For the Peripheral bit-band region: Alias address = 0x42000000 + (byte_offset x 32) + (bit_number x 4). The x32 factor comes from 8 bits per byte times 4 bytes per alias word. This formula is directly tested in GATE exams.

Practical Understanding

On an STM32F4, the GPIOA output data register (ODR) is located at 0x40020014. This address falls within the Peripheral bit-band region. Bit 5 of GPIOA ODR controls pin PA5 (the onboard LED on Nucleo boards). The bit-band alias address for this bit allows toggling PA5 with a single 32-bit write, which is atomic. This eliminates the risk of an interrupt corrupting the GPIO state between the read and write operations of a standard read-modify-write sequence.

Given:
GPIOA ODR address: 0x40020014
Bit to access: bit 5 (PA5 LED pin)
Peripheral bit-band alias base: 0x42000000

Why this formula applies:
Bit-band maps each bit to a 32-bit alias word for atomic single-bit access.

Formula:
byte_offset = target_address - 0x40000000
Alias = 0x42000000 + (byte_offset x 32) + (bit_number x 4)

Substitution:
byte_offset = 0x40020014 - 0x40000000 = 0x00020014 = 131092 decimal
Alias = 0x42000000 + (131092 x 32) + (5 x 4)

Calculation:
131092 x 32 = 4,194,944 = 0x400280
Alias = 0x42000000 + 0x400280 + 0x14
Alias = 0x42400294

Final Answer:
Writing 0x00000001 to address 0x42400294 atomically sets PA5 high.
Writing 0x00000000 to 0x42400294 atomically clears PA5 low.

Exam Tip: The bit-band alias formula is a high-frequency GATE topic. Memorize: Alias = Alias_Base + (byte_offset x 32) + (bit x 4). For SRAM alias base is 0x22000000, for Peripheral alias base is 0x42000000. The x32 = 8 bits x 4 bytes. The PPB addresses (NVIC at 0xE000E100, SCB at 0xE000ED00) are the same on all Cortex-M devices.

Mechanism: Memory Regions and Bus Mapping

• Code region uses the I-Code bus for instruction fetch and D-Code bus for constant data. It is the only region that benefits from the Harvard-like dual-bus access optimization.
• SRAM region is accessible via the System bus. It supports bit-banding in the first 1 MB, with the alias mapped to 0x22000000. SRAM code execution is possible but slower without prefetch optimization.
• Peripheral region registers are accessed via the System bus through the AHB-to-APB bridge. The first 1 MB supports bit-banding with the alias at 0x42000000, enabling atomic single-bit peripheral register access.
• PPB region (0xE0000000 onwards) is strictly privileged-access only. Unprivileged code (RTOS tasks) attempting to access SysTick or NVIC directly will trigger a HardFault or BusFault.
• VTOR (Vector Table Offset Register) at 0xE000ED08 in the SCB allows relocating the vector table from its default Code region location to any 512-byte aligned address, enabling booting from bootloaders and applications in SRAM.

Quick Revision

• 4 GB space split into 8 fixed 512 MB regions: Code, SRAM, Peripheral, Ext RAM, Ext Device, reserved, PPB.
• Code region: 0x00000000. SRAM: 0x20000000. Peripheral: 0x40000000. PPB: 0xE0000000. These boundaries are fixed in ARMv7-M.
• Bit-band alias formula: Alias = Alias_base + (byte_offset x 32) + (bit_num x 4). SRAM alias base = 0x22000000. Peripheral alias base = 0x42000000.
• PPB fixed system addresses: SysTick at 0xE000E010, NVIC at 0xE000E100, SCB at 0xE000ED00, MPU at 0xE000ED90. Same on all Cortex-M MCUs.
• Accessing the Code region for data uses D-Code bus. Accessing SRAM for data uses System bus. They do not conflict.
• Exam trap: PPB is accessible only in privileged mode. An RTOS task running in unprivileged Thread mode cannot directly read NVIC or SysTick registers. It must use SVC calls.
• Bit-banding provides atomic bit operations without disabling interrupts, critical for thread-safe peripheral register manipulation.