VLSI Design
MOS Capacitor Structure
Accumulation, depletion, inversion modes.
Threshold Voltage
Expressions, body effect.
NMOS/PMOS I-V
Cutoff, linear, saturation regions.
Channel Length Modulation
Finite output impedance.
Subthreshold Conduction
Leakage current below Vt.
MOS Capacitances
Cgs, Cgd, Cdb, Csb, Cox.
Velocity Saturation
Short channel effect explanation.
CMOS Inverter
VTC, noise margins, switching threshold.
CMOS NAND/NOR
Series/Parallel transistor sizing.
Complex Gates
AOI and OAI logic realization.
Pass Transistor Logic
Signal degradation, threshold drop.
Transmission Gates
Perfect switch, resistance analysis.
Tri-State Buffers
High, Low, High-Z states.
Elmore Delay
RC delay estimation.
Carry Skip/Select
Adder optimization architectures.
CMOS Multipliers
Array multiplier, Wallace tree multiplier basics.
Transmission Gate Logic
XOR, Multiplexer implementation using TGs.
Barrel Shifter
Shifting logic using pass transistors.
Domino Logic Circuits
Precharge/Evaluate phases, cascade issues.
Level Shifters
Interfacing different voltage domains.
IO Pads
Input/Output buffers, ESD protection.
D Latch
Level sensitive latch, transmission gate implementation.
D Flip-Flop
Master-Slave edge triggered register.
JK Flip-Flop CMOS
Implementation details.
Setup and Hold Time
Timing constraints, calculating T_clk.
Synchronizers
Handling asynchronous inputs.
DRAM Refresh
Need for periodic refresh.
ROM/PROM Design
Nor-based and Nand-based ROMs.
Flash Memory Cell
Floating gate transistor.
VLSI Design Flow
Y-Chart, specification to layout steps.
Design Entry
Schematic vs HDL.
DRC LVS
Design Rule Check, Layout Vs Schematic.
Parasitic Extraction
R and C extraction for post-layout sim.
Power Components
Dynamic, Short-circuit, Leakage power.
Dynamic Power Reduction
Clock gating, voltage scaling.
Leakage Power Reduction
High-k dielectrics, multi-Vt.
DVFS
Dynamic Voltage and Frequency Scaling.
FinFET Technology
3D transistors, advantages over planar.
SOI Technology
Silicon On Insulator benefits.
FPGA Architecture Elements
LUT, CLB, Switch Matrix.
Hot Carrier Effect
Reliability issues.
SR Latch
NOR and NAND based latches.
Logical Effort
Delay optimization technique.
CMOS Adders
Ripple carry, Carry lookahead, Manchester carry chain in CMOS.
Booth Multiplier
Algorithm for signed multiplication.
Bistability Principle
Inverter loop, metastability.
Clock Skew and Jitter
Impact on timing, H-tree clock distribution.
Power Gating
Sleep transistors, MTCMOS.
SRAM 6T Cell
Read stability, write ability.
SRAM Array Org
Row decoders, column muxing.
DRAM 1T Cell
Charge storage, capacitive sensing.
Sense Amplifiers
Differential sensing, precharging bitlines.
Lambda Rules
Scalable design rules, stick diagrams.
Layout Basics
Active, poly, metal layers, contacts.
Design for Testability
Scan chains, BIST, boundary scan.
Fault Models
Stuck-at faults, delay faults.