Digital Electronics
K-Map 3 Variable
3-variable K-map, adjacency, grouping 1s 2s 4s.
1-to-4 Demultiplexer
Single input to multiple outputs, enable control.
Carry Lookahead Adder
Generate and propagate, fast carry computation, CLA.
MUX as Function Generator
Implementing Boolean functions using multiplexers.
K-Map 4 Variable
4-variable K-map, wrapping, corner groups.
K-Map POS Simplification
Grouping 0s to obtain simplified POS form.
Hamming Code
Error correction, redundant bits, syndrome calculation.
3-to-8 Decoder
IC 74138, enable inputs, function implementation.
BCD to 7-Segment Decoder
IC 7447, display driver, segment mapping.
SR Flip-Flop
Edge triggered SR, characteristic equation, excitation table.
D Flip-Flop
Data flip-flop, no invalid state, transparent latch vs edge.
2-to-4 Decoder
Enable input, active high and active low outputs.
Parity Generator
Even and odd parity generation circuit.
Parity Checker
Error detection using parity checking.
SR Latch
NOR gate latch, NAND gate latch, invalid state.
JK Flip-Flop
Toggle on J=K=1, master-slave, race condition solution.
T Flip-Flop
Toggle flip-flop, T=1 toggles, frequency division.
Asynchronous Counter
Ripple counter, propagation delay accumulation.
SISO Shift Register
Serial in serial out, data shifting, delay line.
Flip-Flop Conversions
SR to JK, JK to D, JK to T using excitation tables.
Synchronous Counter
Common clock, simultaneous switching, faster operation.
BCD Counter
Mod-10 counter, 0000 to 1001, auto reset.
Up Down Counter
Bidirectional counting, control input for direction.
Flip-Flop Timing Parameters
Setup time, hold time, propagation delay, clock-to-Q.
ROM Architecture
Read only memory, address decoder, fixed data storage.
PROM
Programmable ROM, fusible links, one-time programming.
SRAM vs DRAM
Speed, density, cost, power comparison.
Flash Memory
NAND and NOR flash, page and block operations.
PLA
Programmable logic array, programmable AND and OR planes.
PAL
Programmable array logic, programmable AND fixed OR.
Moore State Machine
Output depends only on state, more stable outputs.
State Machine Design
State diagram, state table, next state logic derivation.
State Reduction
Equivalent states, row matching, implication table.
Sequence Detector Design
Overlapping and non-overlapping sequence detection.
Propagation Delay
Gate delay, path delay, critical path identification.
FPGA Architecture
Look-up tables, CLBs, IOBs, routing resources.
Synchronous Design Principles
Single clock domain, pipelining, timing closure.
De Morgan Applications
Multi-variable De Morgan, bubble pushing, gate conversion.
Logic Level Interfacing
TTL to CMOS, CMOS to TTL level shifting.
K-Map Don't Care Conditions
Using don't cares for further simplification.
Prime Implicant Chart
Petrick method, covering problem, minimum cover.
Binary Multiplier
Array multiplier, partial products, combinational multiplier.
Priority Encoder
Multiple inputs, highest priority output, valid bit.
8-to-3 Encoder
Octal to binary encoder, active high inputs.
1-to-8 Demultiplexer
Three select lines, data distribution.
Setup and Hold Time
Timing constraints, timing violations, metastability.
Static Hazards
Static-1 and static-0 hazards, detection, elimination.
Code Converter Circuits
BCD to Gray, Gray to BCD, BCD to Excess-3 circuits.
EPROM and EEPROM
UV erasable, electrically erasable, Flash memory basics.
SRAM
Static RAM, 6T cell, fast access, volatile.
DRAM
Dynamic RAM, 1T1C cell, refresh requirement, higher density.
Gated SR Latch
Enable controlled SR latch, clock gating.
Multi-Input Gates
3-input, 4-input gates, cascading for more inputs.
Buffer Gate
Non-inverting buffer, tri-state buffer, bus applications.
PISO Shift Register
Parallel in serial out, parallel to serial conversion.
PIPO Shift Register
Parallel in parallel out, temporary storage.
Universal Shift Register
Bidirectional, all four modes, IC 74194.
Mealy State Machine
Output depends on state and input, faster response.
Shift Register Applications
Sequence generator, pseudo random, serial arithmetic.
State Assignment
Binary, Gray, one-hot encoding, effect on complexity.
CPLD
Complex PLD, macrocells, interconnect matrix.
Dynamic Hazards
Multiple output transitions, causes and prevention.
Glitches and Races
Race conditions, essential hazards in async circuits.
FPGA vs ASIC
Comparison of programmable vs custom IC approaches.
Ring Counter
Circular shift register, one-hot state encoding.
Johnson Counter
Twisted ring counter, 2N states from N flip-flops.
SIPO Shift Register
Serial in parallel out, serial to parallel conversion.
Clock Skew and Jitter
Clock distribution, skew effects, jitter sources.
Asynchronous Circuit Design
Handshake protocols, self-timed circuits.
ASCII Code
7-bit character encoding, printable and control characters.
Error Detection Codes
Parity bit, even and odd parity, error detection.
AND Gate
Two input AND, truth table, Boolean expression Y=AB, IC 7408.
BCD Adder
4-bit BCD addition, correction logic for invalid BCD.
Magnitude Comparator
A>B, A=B, A<B outputs, cascading comparators.
Mod-N Counter
Arbitrary modulus counter design, feedback reset logic.
Binary Number System
Base-2, place values, binary to decimal conversion.
Octal Number System
Base-8, octal to binary and decimal conversion.
Hexadecimal Number System
Base-16, hex to binary and decimal conversion.
Binary Addition
Rules of binary addition, carry propagation.
Binary Subtraction
Direct subtraction and complement methods.
Number System Conversions
Direct methods between binary, octal, decimal, hex.
1s Complement
Bitwise inversion, subtraction using 1s complement.
2s Complement
1s complement + 1, subtraction, overflow detection.
Gray Code
Reflected binary code, binary to Gray conversion.
Excess-3 Code
Self complementing code, BCD to Excess-3 conversion.
Signed Number Representation
Sign magnitude, 1s complement, 2s complement, range.
BCD Code
Binary coded decimal, valid and invalid BCD, BCD addition.
OR Gate
Two input OR, truth table, Boolean expression Y=A+B, IC 7432.
NOT Gate
Inverter, truth table, Boolean expression Y=A', IC 7404.
NAND Gate
Universal gate, truth table, Y=(AB)', IC 7400.
NOR Gate
Universal gate, truth table, Y=(A+B)', IC 7402.
XOR Gate
Exclusive OR, truth table, Y=A xor B, IC 7486.
XNOR Gate
Exclusive NOR, equivalence gate, Y=(A xor B)'.
CMOS Logic Family
Complementary MOS, low power, high noise margin.
Universal Gates NAND
Implementing AND OR NOT using only NAND gates.
Universal Gates NOR
Implementing AND OR NOT using only NOR gates.
TTL Logic Family
Transistor-transistor logic, voltage levels, fan-out, speed.
Boolean Algebra Axioms
Identity, complement, commutative, associative laws.
Boolean Algebra Theorems
Absorption, consensus, idempotent, involution theorems.
De Morgan Theorem 1
Complement of product equals sum of complements (AB)' = A'+B'.
TTL vs CMOS Comparison
Speed, power, noise margin, voltage levels comparison.
De Morgan Theorem 2
Complement of sum equals product of complements (A+B)' = A'B'.
Canonical SOP Form
Sum of products, minterms, canonical representation.
Minterm and Maxterm Relationship
Conversion between SOP and POS, complement relation.
Boolean Expression Simplification
Algebraic simplification step by step examples.
Canonical POS Form
Product of sums, maxterms, canonical representation.
K-Map 2 Variable
2-variable Karnaugh map, grouping rules, simplified expression.
Half Adder
Single bit addition, sum and carry outputs, XOR and AND.
Full Adder
Three input adder, carry in, truth table, implementation.
Ripple Carry Adder
Cascaded full adders, carry propagation delay.
Quine-McCluskey Method
Tabular minimization, prime implicants, essential PIs.
Half Subtractor
Single bit subtraction, difference and borrow outputs.
4-to-1 Multiplexer
Two select lines, function implementation using MUX.
Full Subtractor
Three input subtractor, borrow in, implementation.
8-to-1 Multiplexer
Three select lines, cascading for larger MUX.
2-to-1 Multiplexer
Single select line, data routing, Boolean implementation.